PWM Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: bbf435ceff

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 6.000s 563.312us 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 4.000s 17.381us 5 5 100.00
V1 csr_rw pwm_csr_rw 4.000s 24.323us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 11.000s 1.595ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 5.000s 85.478us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 4.000s 60.093us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 4.000s 24.323us 20 20 100.00
pwm_csr_aliasing 5.000s 85.478us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 2.200m 41.992ms 49 50 98.00
V2 pulse pwm_rand_output 2.200m 41.992ms 49 50 98.00
V2 blink pwm_rand_output 2.200m 41.992ms 49 50 98.00
V2 heartbeat pwm_rand_output 2.200m 41.992ms 49 50 98.00
V2 resolution pwm_rand_output 2.200m 41.992ms 49 50 98.00
V2 multi_channel pwm_rand_output 2.200m 41.992ms 49 50 98.00
V2 polarity pwm_rand_output 2.200m 41.992ms 49 50 98.00
V2 phase pwm_rand_output 2.200m 41.992ms 49 50 98.00
V2 lowpower pwm_rand_output 2.200m 41.992ms 49 50 98.00
V2 perf pwm_perf 54.000s 22.340ms 50 50 100.00
V2 stress_all pwm_stress_all 3.617m 110.442ms 47 50 94.00
V2 alert_test pwm_alert_test 7.000s 41.391us 50 50 100.00
V2 intr_test pwm_intr_test 4.000s 14.321us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 6.000s 570.620us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 6.000s 570.620us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 4.000s 17.381us 5 5 100.00
pwm_csr_rw 4.000s 24.323us 20 20 100.00
pwm_csr_aliasing 5.000s 85.478us 5 5 100.00
pwm_same_csr_outstanding 4.000s 63.451us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 4.000s 17.381us 5 5 100.00
pwm_csr_rw 4.000s 24.323us 20 20 100.00
pwm_csr_aliasing 5.000s 85.478us 5 5 100.00
pwm_same_csr_outstanding 4.000s 63.451us 20 20 100.00
V2 TOTAL 286 290 98.62
V2S tl_intg_err pwm_tl_intg_err 5.000s 151.116us 20 20 100.00
pwm_sec_cm 3.000s 134.052us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 5.000s 151.116us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 416 420 99.05

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 5 71.43
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.32 99.38 98.89 99.76 94.65 94.92 -- 100.00 99.01

Failure Buckets

Past Results