bbf435ceff
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwm_smoke | 6.000s | 563.312us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwm_csr_hw_reset | 4.000s | 17.381us | 5 | 5 | 100.00 |
V1 | csr_rw | pwm_csr_rw | 4.000s | 24.323us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwm_csr_bit_bash | 11.000s | 1.595ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwm_csr_aliasing | 5.000s | 85.478us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 60.093us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 4.000s | 24.323us | 20 | 20 | 100.00 |
pwm_csr_aliasing | 5.000s | 85.478us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | dutycycle | pwm_rand_output | 2.200m | 41.992ms | 49 | 50 | 98.00 |
V2 | pulse | pwm_rand_output | 2.200m | 41.992ms | 49 | 50 | 98.00 |
V2 | blink | pwm_rand_output | 2.200m | 41.992ms | 49 | 50 | 98.00 |
V2 | heartbeat | pwm_rand_output | 2.200m | 41.992ms | 49 | 50 | 98.00 |
V2 | resolution | pwm_rand_output | 2.200m | 41.992ms | 49 | 50 | 98.00 |
V2 | multi_channel | pwm_rand_output | 2.200m | 41.992ms | 49 | 50 | 98.00 |
V2 | polarity | pwm_rand_output | 2.200m | 41.992ms | 49 | 50 | 98.00 |
V2 | phase | pwm_rand_output | 2.200m | 41.992ms | 49 | 50 | 98.00 |
V2 | lowpower | pwm_rand_output | 2.200m | 41.992ms | 49 | 50 | 98.00 |
V2 | perf | pwm_perf | 54.000s | 22.340ms | 50 | 50 | 100.00 |
V2 | stress_all | pwm_stress_all | 3.617m | 110.442ms | 47 | 50 | 94.00 |
V2 | alert_test | pwm_alert_test | 7.000s | 41.391us | 50 | 50 | 100.00 |
V2 | intr_test | pwm_intr_test | 4.000s | 14.321us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 570.620us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 570.620us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 4.000s | 17.381us | 5 | 5 | 100.00 |
pwm_csr_rw | 4.000s | 24.323us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 5.000s | 85.478us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 4.000s | 63.451us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwm_csr_hw_reset | 4.000s | 17.381us | 5 | 5 | 100.00 |
pwm_csr_rw | 4.000s | 24.323us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 5.000s | 85.478us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 4.000s | 63.451us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 286 | 290 | 98.62 | |||
V2S | tl_intg_err | pwm_tl_intg_err | 5.000s | 151.116us | 20 | 20 | 100.00 |
pwm_sec_cm | 3.000s | 134.052us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 5.000s | 151.116us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 416 | 420 | 99.05 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 7 | 7 | 5 | 71.43 |
V2S | 2 | 2 | 2 | 100.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.32 | 99.38 | 98.89 | 99.76 | 94.65 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard]
has 4 failures:
Test pwm_rand_output has 1 failures.
3.pwm_rand_output.93650360749524245022758558339240569870292297656571794594445214983934120646249
Line 122132, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/3.pwm_rand_output/latest/run.log
UVM_ERROR @ 311767211 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [1] did not MATCH
UVM_INFO @ 311767211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test pwm_stress_all has 3 failures.
20.pwm_stress_all.59955310647604462478466614441061957535248850239609069342697492763876171843155
Line 3417, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/20.pwm_stress_all/latest/run.log
UVM_ERROR @ 12075593079 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [5] did not MATCH
UVM_INFO @ 12075593079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.pwm_stress_all.80769392010153574892686600934537917969735203136182787018624305451254535826433
Line 1317, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/23.pwm_stress_all/latest/run.log
UVM_ERROR @ 161389224038 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [5] did not MATCH
UVM_INFO @ 161389224038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.