PWM Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: `3707c48f56`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	6.000s	1.020ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	102.124us	5	5	100.00
V1	csr_rw	pwm_csr_rw	7.000s	254.440us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	11.000s	685.671us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	3.000s	113.127us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	32.515us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	7.000s	254.440us	20	20	100.00
		pwm_csr_aliasing	3.000s	113.127us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.367m	47.716ms	49	50	98.00
V2	pulse	pwm_rand_output	1.367m	47.716ms	49	50	98.00
V2	blink	pwm_rand_output	1.367m	47.716ms	49	50	98.00
V2	heartbeat	pwm_rand_output	1.367m	47.716ms	49	50	98.00
V2	resolution	pwm_rand_output	1.367m	47.716ms	49	50	98.00
V2	multi_channel	pwm_rand_output	1.367m	47.716ms	49	50	98.00
V2	polarity	pwm_rand_output	1.367m	47.716ms	49	50	98.00
V2	phase	pwm_rand_output	1.367m	47.716ms	49	50	98.00
V2	lowpower	pwm_rand_output	1.367m	47.716ms	49	50	98.00
V2	perf	pwm_perf	50.000s	21.430ms	49	50	98.00
V2	stress_all	pwm_stress_all	5.717m	222.895ms	48	50	96.00
V2	alert_test	pwm_alert_test	4.000s	94.427us	50	50	100.00
V2	intr_test	pwm_intr_test	7.000s	31.426us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	6.000s	464.962us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	6.000s	464.962us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	102.124us	5	5	100.00
		pwm_csr_rw	7.000s	254.440us	20	20	100.00
		pwm_csr_aliasing	3.000s	113.127us	5	5	100.00
		pwm_same_csr_outstanding	7.000s	29.621us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	102.124us	5	5	100.00
		pwm_csr_rw	7.000s	254.440us	20	20	100.00
		pwm_csr_aliasing	3.000s	113.127us	5	5	100.00
		pwm_same_csr_outstanding	7.000s	29.621us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	pwm_tl_intg_err	9.000s	135.310us	20	20	100.00
		pwm_sec_cm	5.000s	85.216us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	9.000s	135.310us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			416	420	99.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	4	57.14
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.54	99.48	99.08	99.96	95.13	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

14.pwm_stress_all.85662602838100426982109017135950646117885755667815419550569457065315047815075
Line 210896, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/14.pwm_stress_all/latest/run.log

  UVM_ERROR @ 270529343565 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 270529343565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.pwm_stress_all.68000262658720406608767547078439937722418174908999822170102461069631594577521
Line 658, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/45.pwm_stress_all/latest/run.log

  UVM_ERROR @ 21009310386 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [3] did not MATCH
  UVM_INFO @ 21009310386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test pwm_perf has 1 failures.
  - 25.pwm_perf.44572287854394175187259560970088494111647152749624419464281606359511909652732
    Line 375, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/25.pwm_perf/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test pwm_rand_output has 1 failures.
  - 47.pwm_rand_output.54829632625253741606696129621143601766223267550128477770782393821563755675480
    Line 403, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/47.pwm_rand_output/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```