07b417ef03| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 6.000s | 2.035ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 4.000s | 35.624us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 4.000s | 17.533us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 12.000s | 458.703us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 7.000s | 303.144us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 7.000s | 21.688us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 4.000s | 17.533us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 7.000s | 303.144us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.583m | 43.750ms | 48 | 50 | 96.00 |
| V2 | pulse | pwm_rand_output | 1.583m | 43.750ms | 48 | 50 | 96.00 |
| V2 | blink | pwm_rand_output | 1.583m | 43.750ms | 48 | 50 | 96.00 |
| V2 | heartbeat | pwm_rand_output | 1.583m | 43.750ms | 48 | 50 | 96.00 |
| V2 | resolution | pwm_rand_output | 1.583m | 43.750ms | 48 | 50 | 96.00 |
| V2 | multi_channel | pwm_rand_output | 1.583m | 43.750ms | 48 | 50 | 96.00 |
| V2 | polarity | pwm_rand_output | 1.583m | 43.750ms | 48 | 50 | 96.00 |
| V2 | phase | pwm_rand_output | 1.583m | 43.750ms | 48 | 50 | 96.00 |
| V2 | lowpower | pwm_rand_output | 1.583m | 43.750ms | 48 | 50 | 96.00 |
| V2 | perf | pwm_perf | 52.000s | 10.610ms | 50 | 50 | 100.00 |
| V2 | stress_all | pwm_stress_all | 4.383m | 63.000ms | 47 | 50 | 94.00 |
| V2 | alert_test | pwm_alert_test | 4.000s | 16.129us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 5.000s | 14.706us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 194.612us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 194.612us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 4.000s | 35.624us | 5 | 5 | 100.00 |
| pwm_csr_rw | 4.000s | 17.533us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 7.000s | 303.144us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 5.000s | 27.155us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 4.000s | 35.624us | 5 | 5 | 100.00 |
| pwm_csr_rw | 4.000s | 17.533us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 7.000s | 303.144us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 5.000s | 27.155us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 285 | 290 | 98.28 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 6.000s | 170.719us | 20 | 20 | 100.00 |
| pwm_sec_cm | 3.000s | 38.810us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 6.000s | 170.719us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 415 | 420 | 98.81 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.47 | 99.52 | 99.14 | 99.92 | 94.79 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 3 failures:
17.pwm_stress_all.71130301352740676874714295663193456967087875865341907940007126558378321238198
Line 1259010, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/17.pwm_stress_all/latest/run.log
UVM_ERROR @ 42416905609 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 42416905609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.pwm_stress_all.3543057744759954273103133261258570039490371776306417525642928367841685666525
Line 559927, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/22.pwm_stress_all/latest/run.log
UVM_ERROR @ 21041282990 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [1] did not MATCH
UVM_INFO @ 21041282990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
36.pwm_rand_output.21962180757070874102861597225098794783428916169002305815861401606748642161828
Line 352, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/36.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.pwm_rand_output.99785808704170710449695506239574668011592218976573235123425083833893430125644
Line 787, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/38.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---