PWM Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 10.000s 2.033ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 2.000s 35.371us 5 5 100.00
V1 csr_rw pwm_csr_rw 12.000s 60.678us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 15.000s 6.404ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 11.000s 85.636us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 7.000s 98.341us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 12.000s 60.678us 20 20 100.00
pwm_csr_aliasing 11.000s 85.636us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.817m 47.736ms 50 50 100.00
V2 pulse pwm_rand_output 1.817m 47.736ms 50 50 100.00
V2 blink pwm_rand_output 1.817m 47.736ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.817m 47.736ms 50 50 100.00
V2 resolution pwm_rand_output 1.817m 47.736ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.817m 47.736ms 50 50 100.00
V2 polarity pwm_rand_output 1.817m 47.736ms 50 50 100.00
V2 phase pwm_rand_output 1.817m 47.736ms 50 50 100.00
V2 lowpower pwm_rand_output 1.817m 47.736ms 50 50 100.00
V2 perf pwm_perf 57.000s 20.594ms 50 50 100.00
V2 stress_all pwm_stress_all 5.317m 31.852ms 50 50 100.00
V2 alert_test pwm_alert_test 7.000s 82.817us 50 50 100.00
V2 intr_test pwm_intr_test 12.000s 32.655us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 14.000s 37.381us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 14.000s 37.381us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 2.000s 35.371us 5 5 100.00
pwm_csr_rw 12.000s 60.678us 20 20 100.00
pwm_csr_aliasing 11.000s 85.636us 5 5 100.00
pwm_same_csr_outstanding 13.000s 183.388us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 2.000s 35.371us 5 5 100.00
pwm_csr_rw 12.000s 60.678us 20 20 100.00
pwm_csr_aliasing 11.000s 85.636us 5 5 100.00
pwm_same_csr_outstanding 13.000s 183.388us 20 20 100.00
V2 TOTAL 290 290 100.00
V2S tl_intg_err pwm_tl_intg_err 19.000s 207.162us 20 20 100.00
pwm_sec_cm 3.000s 67.832us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 19.000s 207.162us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 420 420 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 7 100.00
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.31 99.34 98.83 99.84 94.55 94.92 -- 100.00 99.01

Past Results