PWM Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 9.000s 535.044us 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 13.380us 5 5 100.00
V1 csr_rw pwm_csr_rw 7.000s 21.813us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 12.000s 266.853us 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 3.000s 98.580us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 4.000s 62.580us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 7.000s 21.813us 20 20 100.00
pwm_csr_aliasing 3.000s 98.580us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.250m 20.197ms 50 50 100.00
V2 pulse pwm_rand_output 1.250m 20.197ms 50 50 100.00
V2 blink pwm_rand_output 1.250m 20.197ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.250m 20.197ms 50 50 100.00
V2 resolution pwm_rand_output 1.250m 20.197ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.250m 20.197ms 50 50 100.00
V2 polarity pwm_rand_output 1.250m 20.197ms 50 50 100.00
V2 phase pwm_rand_output 1.250m 20.197ms 50 50 100.00
V2 lowpower pwm_rand_output 1.250m 20.197ms 50 50 100.00
V2 perf pwm_perf 51.000s 58.332ms 49 50 98.00
V2 stress_all pwm_stress_all 9.133m 73.960ms 50 50 100.00
V2 alert_test pwm_alert_test 7.000s 46.615us 50 50 100.00
V2 intr_test pwm_intr_test 8.000s 37.601us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 6.000s 393.191us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 6.000s 393.191us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 13.380us 5 5 100.00
pwm_csr_rw 7.000s 21.813us 20 20 100.00
pwm_csr_aliasing 3.000s 98.580us 5 5 100.00
pwm_same_csr_outstanding 8.000s 120.337us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 13.380us 5 5 100.00
pwm_csr_rw 7.000s 21.813us 20 20 100.00
pwm_csr_aliasing 3.000s 98.580us 5 5 100.00
pwm_same_csr_outstanding 8.000s 120.337us 20 20 100.00
V2 TOTAL 289 290 99.66
V2S tl_intg_err pwm_tl_intg_err 6.000s 538.772us 20 20 100.00
pwm_sec_cm 3.000s 134.372us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 6.000s 538.772us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 419 420 99.76

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.39 99.38 98.89 99.72 95.03 94.92 -- 100.00 99.01

Failure Buckets

Past Results