098010d125| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 6.000s | 535.713us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 2.000s | 24.200us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 3.000s | 82.475us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 9.000s | 2.278ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 3.000s | 162.696us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 125.371us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 82.475us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 3.000s | 162.696us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.000m | 20.194ms | 48 | 50 | 96.00 |
| V2 | pulse | pwm_rand_output | 1.000m | 20.194ms | 48 | 50 | 96.00 |
| V2 | blink | pwm_rand_output | 1.000m | 20.194ms | 48 | 50 | 96.00 |
| V2 | heartbeat | pwm_rand_output | 1.000m | 20.194ms | 48 | 50 | 96.00 |
| V2 | resolution | pwm_rand_output | 1.000m | 20.194ms | 48 | 50 | 96.00 |
| V2 | multi_channel | pwm_rand_output | 1.000m | 20.194ms | 48 | 50 | 96.00 |
| V2 | polarity | pwm_rand_output | 1.000m | 20.194ms | 48 | 50 | 96.00 |
| V2 | phase | pwm_rand_output | 1.000m | 20.194ms | 48 | 50 | 96.00 |
| V2 | lowpower | pwm_rand_output | 1.000m | 20.194ms | 48 | 50 | 96.00 |
| V2 | perf | pwm_perf | 54.000s | 10.506ms | 50 | 50 | 100.00 |
| V2 | stress_all | pwm_stress_all | 4.033m | 308.322ms | 46 | 50 | 92.00 |
| V2 | alert_test | pwm_alert_test | 12.000s | 21.167us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 3.000s | 18.631us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 120.542us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 120.542us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 2.000s | 24.200us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 82.475us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 3.000s | 162.696us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 3.000s | 107.170us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 2.000s | 24.200us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 82.475us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 3.000s | 162.696us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 3.000s | 107.170us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 284 | 290 | 97.93 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 5.000s | 1.154ms | 20 | 20 | 100.00 |
| pwm_sec_cm | 3.000s | 270.602us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 5.000s | 1.154ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 414 | 420 | 98.57 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.19 | 99.14 | 98.46 | 99.80 | 94.45 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 4 failures:
6.pwm_stress_all.105209492288302752989715516443163122351338768530064840138837942832009999579289
Line 699194, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/6.pwm_stress_all/latest/run.log
UVM_ERROR @ 27808697492 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [1] did not MATCH
UVM_INFO @ 27808697492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.pwm_stress_all.42719297010809910020192806502969320760814353639942641124848060183254823487211
Line 838, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/28.pwm_stress_all/latest/run.log
UVM_ERROR @ 216693498782 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [3] did not MATCH
UVM_INFO @ 216693498782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
16.pwm_rand_output.48689089497204613875784869781776996903947697601480393877930072718251339887942
Line 400, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/16.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.pwm_rand_output.102316146838130333174488090371979062713748824856280992241574695179909046177939
Line 1424, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/18.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---