PWM Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: `584c3d46af`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	518.689us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	24.419us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	73.840us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	12.000s	3.579ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	5.000s	34.348us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	3.000s	102.116us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	73.840us	20	20	100.00
		pwm_csr_aliasing	5.000s	34.348us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.833m	11.056ms	50	50	100.00
V2	pulse	pwm_rand_output	1.833m	11.056ms	50	50	100.00
V2	blink	pwm_rand_output	1.833m	11.056ms	50	50	100.00
V2	heartbeat	pwm_rand_output	1.833m	11.056ms	50	50	100.00
V2	resolution	pwm_rand_output	1.833m	11.056ms	50	50	100.00
V2	multi_channel	pwm_rand_output	1.833m	11.056ms	50	50	100.00
V2	polarity	pwm_rand_output	1.833m	11.056ms	50	50	100.00
V2	phase	pwm_rand_output	1.833m	11.056ms	50	50	100.00
V2	lowpower	pwm_rand_output	1.833m	11.056ms	50	50	100.00
V2	perf	pwm_perf	50.000s	43.745ms	50	50	100.00
V2	stress_all	pwm_stress_all	4.083m	297.284ms	48	50	96.00
V2	alert_test	pwm_alert_test	4.000s	14.949us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	54.291us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	6.000s	90.350us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	6.000s	90.350us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	24.419us	5	5	100.00
		pwm_csr_rw	3.000s	73.840us	20	20	100.00
		pwm_csr_aliasing	5.000s	34.348us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	151.342us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	24.419us	5	5	100.00
		pwm_csr_rw	3.000s	73.840us	20	20	100.00
		pwm_csr_aliasing	5.000s	34.348us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	151.342us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	337.110us	20	20	100.00
		pwm_sec_cm	4.000s	242.380us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	337.110us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.56	99.55	99.20	99.88	95.20	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

18.pwm_stress_all.113827239314863007014493752954277161811448875822183933356931125952424021906119
Line 743, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/18.pwm_stress_all/latest/run.log

  UVM_ERROR @ 135440167578 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 135440167578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.pwm_stress_all.96369193900706791215599279273968781104667058308630154029083680200048948722941
Line 855, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/26.pwm_stress_all/latest/run.log

  UVM_ERROR @ 32826876357 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 32826876357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---