PWM Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: `d09e282b26`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	3.402ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	2.000s	63.393us	5	5	100.00
V1	csr_rw	pwm_csr_rw	8.000s	54.122us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	11.000s	316.938us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	83.942us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	11.000s	33.820us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	8.000s	54.122us	20	20	100.00
		pwm_csr_aliasing	4.000s	83.942us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	3.583m	21.878ms	50	50	100.00
V2	pulse	pwm_rand_output	3.583m	21.878ms	50	50	100.00
V2	blink	pwm_rand_output	3.583m	21.878ms	50	50	100.00
V2	heartbeat	pwm_rand_output	3.583m	21.878ms	50	50	100.00
V2	resolution	pwm_rand_output	3.583m	21.878ms	50	50	100.00
V2	multi_channel	pwm_rand_output	3.583m	21.878ms	50	50	100.00
V2	polarity	pwm_rand_output	3.583m	21.878ms	50	50	100.00
V2	phase	pwm_rand_output	3.583m	21.878ms	50	50	100.00
V2	lowpower	pwm_rand_output	3.583m	21.878ms	50	50	100.00
V2	perf	pwm_perf	51.000s	13.295ms	50	50	100.00
V2	stress_all	pwm_stress_all	4.783m	54.608ms	47	50	94.00
V2	alert_test	pwm_alert_test	3.000s	14.765us	50	50	100.00
V2	intr_test	pwm_intr_test	7.000s	38.415us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	5.000s	230.279us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	5.000s	230.279us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	2.000s	63.393us	5	5	100.00
		pwm_csr_rw	8.000s	54.122us	20	20	100.00
		pwm_csr_aliasing	4.000s	83.942us	5	5	100.00
		pwm_same_csr_outstanding	12.000s	87.756us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	2.000s	63.393us	5	5	100.00
		pwm_csr_rw	8.000s	54.122us	20	20	100.00
		pwm_csr_aliasing	4.000s	83.942us	5	5	100.00
		pwm_same_csr_outstanding	12.000s	87.756us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	289.046us	20	20	100.00
		pwm_sec_cm	3.000s	73.917us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	289.046us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			417	420	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.42	99.41	98.95	99.96	94.72	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 3 failures:

Test pwm_stress_all has 3 failures.

3.pwm_stress_all.82412137172519062949145027566576971654174386724562452988231221725812646748174
Line 456, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/3.pwm_stress_all/latest/run.log

  UVM_ERROR @ 116656377869 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [3] did not MATCH
  UVM_INFO @ 116656377869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.pwm_stress_all.31895448032406643636720268001005139381094479231804159988095057074663229422187
Line 323269, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/7.pwm_stress_all/latest/run.log

  UVM_ERROR @ 46410132980 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [2] did not MATCH
  UVM_INFO @ 46410132980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.