76588857da
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwm_smoke | 10.000s | 1.240ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 13.206us | 5 | 5 | 100.00 |
V1 | csr_rw | pwm_csr_rw | 4.000s | 65.705us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwm_csr_bit_bash | 12.000s | 963.830us | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwm_csr_aliasing | 5.000s | 167.919us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 33.807us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 4.000s | 65.705us | 20 | 20 | 100.00 |
pwm_csr_aliasing | 5.000s | 167.919us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | dutycycle | pwm_rand_output | 1.250m | 10.502ms | 50 | 50 | 100.00 |
V2 | pulse | pwm_rand_output | 1.250m | 10.502ms | 50 | 50 | 100.00 |
V2 | blink | pwm_rand_output | 1.250m | 10.502ms | 50 | 50 | 100.00 |
V2 | heartbeat | pwm_rand_output | 1.250m | 10.502ms | 50 | 50 | 100.00 |
V2 | resolution | pwm_rand_output | 1.250m | 10.502ms | 50 | 50 | 100.00 |
V2 | multi_channel | pwm_rand_output | 1.250m | 10.502ms | 50 | 50 | 100.00 |
V2 | polarity | pwm_rand_output | 1.250m | 10.502ms | 50 | 50 | 100.00 |
V2 | phase | pwm_rand_output | 1.250m | 10.502ms | 50 | 50 | 100.00 |
V2 | lowpower | pwm_rand_output | 1.250m | 10.502ms | 50 | 50 | 100.00 |
V2 | perf | pwm_perf | 50.000s | 10.505ms | 50 | 50 | 100.00 |
V2 | stress_all | pwm_stress_all | 4.567m | 107.158ms | 47 | 50 | 94.00 |
V2 | alert_test | pwm_alert_test | 4.000s | 14.805us | 50 | 50 | 100.00 |
V2 | intr_test | pwm_intr_test | 7.000s | 68.453us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 75.942us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 75.942us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 13.206us | 5 | 5 | 100.00 |
pwm_csr_rw | 4.000s | 65.705us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 5.000s | 167.919us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 3.000s | 50.765us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 13.206us | 5 | 5 | 100.00 |
pwm_csr_rw | 4.000s | 65.705us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 5.000s | 167.919us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 3.000s | 50.765us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 287 | 290 | 98.97 | |||
V2S | tl_intg_err | pwm_tl_intg_err | 6.000s | 471.658us | 20 | 20 | 100.00 |
pwm_sec_cm | 4.000s | 133.447us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 6.000s | 471.658us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 417 | 420 | 99.29 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 7 | 7 | 6 | 85.71 |
V2S | 2 | 2 | 2 | 100.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.34 | 99.38 | 98.89 | 99.76 | 94.76 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard]
has 3 failures:
34.pwm_stress_all.57275455021575328136849650766430979820315234581604797873980129023723521940598
Line 7865, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/34.pwm_stress_all/latest/run.log
UVM_ERROR @ 48465414006 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 48465414006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.pwm_stress_all.105492356092082713808690166192830563279512807751494776607862863887795918211450
Line 131452, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/37.pwm_stress_all/latest/run.log
UVM_ERROR @ 21429018855 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [4] did not MATCH
UVM_INFO @ 21429018855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.