f1535c5540| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 10.000s | 1.816ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 180.458us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 3.000s | 131.008us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 11.000s | 669.108us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 4.000s | 339.049us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 31.568us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 131.008us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 4.000s | 339.049us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.617m | 11.054ms | 49 | 50 | 98.00 |
| V2 | pulse | pwm_rand_output | 1.617m | 11.054ms | 49 | 50 | 98.00 |
| V2 | blink | pwm_rand_output | 1.617m | 11.054ms | 49 | 50 | 98.00 |
| V2 | heartbeat | pwm_rand_output | 1.617m | 11.054ms | 49 | 50 | 98.00 |
| V2 | resolution | pwm_rand_output | 1.617m | 11.054ms | 49 | 50 | 98.00 |
| V2 | multi_channel | pwm_rand_output | 1.617m | 11.054ms | 49 | 50 | 98.00 |
| V2 | polarity | pwm_rand_output | 1.617m | 11.054ms | 49 | 50 | 98.00 |
| V2 | phase | pwm_rand_output | 1.617m | 11.054ms | 49 | 50 | 98.00 |
| V2 | lowpower | pwm_rand_output | 1.617m | 11.054ms | 49 | 50 | 98.00 |
| V2 | perf | pwm_perf | 53.000s | 14.003ms | 49 | 50 | 98.00 |
| V2 | stress_all | pwm_stress_all | 4.367m | 262.471ms | 47 | 50 | 94.00 |
| V2 | alert_test | pwm_alert_test | 7.000s | 128.790us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 3.000s | 15.122us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 8.000s | 155.681us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 8.000s | 155.681us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 180.458us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 131.008us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 339.049us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 3.000s | 100.841us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 180.458us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 131.008us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 339.049us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 3.000s | 100.841us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 285 | 290 | 98.28 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 5.000s | 1.174ms | 20 | 20 | 100.00 |
| pwm_sec_cm | 4.000s | 70.323us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 5.000s | 1.174ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 415 | 420 | 98.81 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 4 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.59 | 99.59 | 99.26 | 99.92 | 95.24 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 3 failures:
0.pwm_stress_all.111332820118468904860765150834122111879934863091519692031288276781876792378691
Line 91980, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/0.pwm_stress_all/latest/run.log
UVM_ERROR @ 64283333854 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [4] did not MATCH
UVM_INFO @ 64283333854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.pwm_stress_all.1585226217673263943488552969012634096016946129926004911187285437371895171138
Line 616, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/16.pwm_stress_all/latest/run.log
UVM_ERROR @ 26116564100 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 26116564100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test pwm_rand_output has 1 failures.
4.pwm_rand_output.48358300468533619851438875755735816542839914533541670638491316711541951537317
Line 5982, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/4.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test pwm_perf has 1 failures.
28.pwm_perf.78118248669378535280207008439249983684051446793974124736929207918059670132439
Line 329, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/28.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---