PWM Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 34.000s 10.152ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 18.106us 5 5 100.00
V1 csr_rw pwm_csr_rw 3.000s 27.173us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 11.000s 2.462ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 4.000s 91.860us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 4.000s 97.972us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 3.000s 27.173us 20 20 100.00
pwm_csr_aliasing 4.000s 91.860us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.433m 43.750ms 50 50 100.00
V2 pulse pwm_rand_output 1.433m 43.750ms 50 50 100.00
V2 blink pwm_rand_output 1.433m 43.750ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.433m 43.750ms 50 50 100.00
V2 resolution pwm_rand_output 1.433m 43.750ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.433m 43.750ms 50 50 100.00
V2 polarity pwm_rand_output 1.433m 43.750ms 50 50 100.00
V2 phase pwm_rand_output 1.433m 43.750ms 50 50 100.00
V2 lowpower pwm_rand_output 1.433m 43.750ms 50 50 100.00
V2 perf pwm_perf 1.467m 43.744ms 50 50 100.00
V2 stress_all pwm_stress_all 5.167m 286.290ms 48 50 96.00
V2 alert_test pwm_alert_test 32.000s 29.507us 50 50 100.00
V2 intr_test pwm_intr_test 3.000s 23.879us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 6.000s 263.235us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 6.000s 263.235us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 18.106us 5 5 100.00
pwm_csr_rw 3.000s 27.173us 20 20 100.00
pwm_csr_aliasing 4.000s 91.860us 5 5 100.00
pwm_same_csr_outstanding 4.000s 103.247us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 18.106us 5 5 100.00
pwm_csr_rw 3.000s 27.173us 20 20 100.00
pwm_csr_aliasing 4.000s 91.860us 5 5 100.00
pwm_same_csr_outstanding 4.000s 103.247us 20 20 100.00
V2 TOTAL 288 290 99.31
V2S tl_intg_err pwm_tl_intg_err 6.000s 264.253us 20 20 100.00
pwm_sec_cm 29.000s 76.279us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 6.000s 264.253us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 418 420 99.52

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.44 99.41 98.95 99.88 94.93 94.92 -- 100.00 99.01

Failure Buckets

Past Results