PWM Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 6.000s 5.082ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 15.924us 5 5 100.00
V1 csr_rw pwm_csr_rw 10.000s 25.003us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 8.000s 264.893us 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 5.000s 175.595us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 7.000s 67.776us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 10.000s 25.003us 20 20 100.00
pwm_csr_aliasing 5.000s 175.595us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.183m 74.990ms 50 50 100.00
V2 pulse pwm_rand_output 1.183m 74.990ms 50 50 100.00
V2 blink pwm_rand_output 1.183m 74.990ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.183m 74.990ms 50 50 100.00
V2 resolution pwm_rand_output 1.183m 74.990ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.183m 74.990ms 50 50 100.00
V2 polarity pwm_rand_output 1.183m 74.990ms 50 50 100.00
V2 phase pwm_rand_output 1.183m 74.990ms 50 50 100.00
V2 lowpower pwm_rand_output 1.183m 74.990ms 50 50 100.00
V2 perf pwm_perf 54.000s 21.005ms 50 50 100.00
V2 stress_all pwm_stress_all 4.333m 174.982ms 49 50 98.00
V2 alert_test pwm_alert_test 3.000s 36.102us 50 50 100.00
V2 intr_test pwm_intr_test 10.000s 21.097us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 12.000s 52.326us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 12.000s 52.326us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 15.924us 5 5 100.00
pwm_csr_rw 10.000s 25.003us 20 20 100.00
pwm_csr_aliasing 5.000s 175.595us 5 5 100.00
pwm_same_csr_outstanding 9.000s 55.814us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 15.924us 5 5 100.00
pwm_csr_rw 10.000s 25.003us 20 20 100.00
pwm_csr_aliasing 5.000s 175.595us 5 5 100.00
pwm_same_csr_outstanding 9.000s 55.814us 20 20 100.00
V2 TOTAL 289 290 99.66
V2S tl_intg_err pwm_tl_intg_err 12.000s 128.533us 20 20 100.00
pwm_sec_cm 3.000s 40.458us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 12.000s 128.533us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 419 420 99.76

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.43 99.38 98.89 99.92 94.89 94.92 -- 100.00 99.01

Failure Buckets

Past Results