e733a8ef8a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 54.000s | 2.043ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 29.000s | 40.012us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 1.567m | 126.350us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 1.167m | 1.051ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 28.000s | 418.732us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 1.600m | 56.805us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 1.567m | 126.350us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 28.000s | 418.732us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 2.200m | 21.875ms | 48 | 50 | 96.00 |
| V2 | pulse | pwm_rand_output | 2.200m | 21.875ms | 48 | 50 | 96.00 |
| V2 | blink | pwm_rand_output | 2.200m | 21.875ms | 48 | 50 | 96.00 |
| V2 | heartbeat | pwm_rand_output | 2.200m | 21.875ms | 48 | 50 | 96.00 |
| V2 | resolution | pwm_rand_output | 2.200m | 21.875ms | 48 | 50 | 96.00 |
| V2 | multi_channel | pwm_rand_output | 2.200m | 21.875ms | 48 | 50 | 96.00 |
| V2 | polarity | pwm_rand_output | 2.200m | 21.875ms | 48 | 50 | 96.00 |
| V2 | phase | pwm_rand_output | 2.200m | 21.875ms | 48 | 50 | 96.00 |
| V2 | lowpower | pwm_rand_output | 2.200m | 21.875ms | 48 | 50 | 96.00 |
| V2 | perf | pwm_perf | 1.983m | 10.719ms | 50 | 50 | 100.00 |
| V2 | stress_all | pwm_stress_all | 6.050m | 222.930ms | 47 | 50 | 94.00 |
| V2 | alert_test | pwm_alert_test | 46.000s | 12.745us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 1.567m | 10.994us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 1.600m | 22.276us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 1.600m | 22.276us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 29.000s | 40.012us | 5 | 5 | 100.00 |
| pwm_csr_rw | 1.567m | 126.350us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 28.000s | 418.732us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 1.483m | 105.489us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 29.000s | 40.012us | 5 | 5 | 100.00 |
| pwm_csr_rw | 1.567m | 126.350us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 28.000s | 418.732us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 1.483m | 105.489us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 285 | 290 | 98.28 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 1.600m | 256.223us | 20 | 20 | 100.00 |
| pwm_sec_cm | 45.000s | 118.963us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 1.600m | 256.223us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 415 | 420 | 98.81 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.34 | 99.31 | 98.77 | 99.84 | 94.76 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 3 failures:
2.pwm_stress_all.10718667619119380412764393885226283984763185144127582908003270043888241967627
Line 10986, in log /workspaces/repo/scratch/os_regression_2024_08_24/pwm-sim-xcelium/2.pwm_stress_all/latest/run.log
UVM_ERROR @ 254368246722 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [5] did not MATCH
UVM_INFO @ 254368246722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.pwm_stress_all.99602140372081424270320313541682829654937872807766497485611612693872604198676
Line 599971, in log /workspaces/repo/scratch/os_regression_2024_08_24/pwm-sim-xcelium/11.pwm_stress_all/latest/run.log
UVM_ERROR @ 91456481654 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [1] did not MATCH
UVM_INFO @ 91456481654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
2.pwm_rand_output.101342417781482818259225250468782878897824791113245942176422231203133601705938
Line 214, in log /workspaces/repo/scratch/os_regression_2024_08_24/pwm-sim-xcelium/2.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.pwm_rand_output.114428929860698639058813702428066174640838187955159706288078039892324099938497
Line 165, in log /workspaces/repo/scratch/os_regression_2024_08_24/pwm-sim-xcelium/35.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---