213e792ea
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwrmgr_smoke | 0.720s | 33.806us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0.680s | 32.662us | 5 | 5 | 100.00 |
V1 | csr_rw | pwrmgr_csr_rw | 0.700s | 21.014us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 3.190s | 223.298us | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwrmgr_csr_aliasing | 0.990s | 167.319us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 1.370s | 102.642us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0.700s | 21.014us | 20 | 20 | 100.00 |
pwrmgr_csr_aliasing | 0.990s | 167.319us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | wakeup | pwrmgr_wakeup | 1.430s | 249.899us | 50 | 50 | 100.00 |
V2 | control_clks | pwrmgr_wakeup | 1.430s | 249.899us | 50 | 50 | 100.00 |
V2 | aborted_low_power | pwrmgr_aborted_low_power | 0.810s | 34.513us | 50 | 50 | 100.00 |
pwrmgr_lowpower_invalid | 0.810s | 45.513us | 50 | 50 | 100.00 | ||
V2 | reset | pwrmgr_reset | 1.420s | 78.601us | 50 | 50 | 100.00 |
pwrmgr_reset_invalid | 1.100s | 93.418us | 50 | 50 | 100.00 | ||
V2 | main_power_glitch_reset | pwrmgr_reset | 1.420s | 78.601us | 50 | 50 | 100.00 |
V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 1.720s | 338.131us | 50 | 50 | 100.00 |
V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 1.370s | 274.194us | 50 | 50 | 100.00 |
V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0.960s | 50.819us | 50 | 50 | 100.00 |
V2 | stress_all | pwrmgr_stress_all | 8.570s | 2.046ms | 50 | 50 | 100.00 |
V2 | intr_test | pwrmgr_intr_test | 0.670s | 21.113us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 2.980s | 60.689us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwrmgr_tl_errors | 2.980s | 60.689us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0.680s | 32.662us | 5 | 5 | 100.00 |
pwrmgr_csr_rw | 0.700s | 21.014us | 20 | 20 | 100.00 | ||
pwrmgr_csr_aliasing | 0.990s | 167.319us | 5 | 5 | 100.00 | ||
pwrmgr_same_csr_outstanding | 0.920s | 144.493us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0.680s | 32.662us | 5 | 5 | 100.00 |
pwrmgr_csr_rw | 0.700s | 21.014us | 20 | 20 | 100.00 | ||
pwrmgr_csr_aliasing | 0.990s | 167.319us | 5 | 5 | 100.00 | ||
pwrmgr_same_csr_outstanding | 0.920s | 144.493us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 540 | 540 | 100.00 | |||
V2S | tl_intg_err | pwrmgr_tl_intg_err | 1.710s | 202.055us | 20 | 20 | 100.00 |
pwrmgr_sec_cm | 2.210s | 702.039us | 5 | 5 | 100.00 | ||
V2S | prim_count_check | pwrmgr_sec_cm | 2.210s | 702.039us | 5 | 5 | 100.00 |
V2S | prim_fsm_check | pwrmgr_sec_cm | 2.210s | 702.039us | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 1.710s | 202.055us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 3.980s | 826.546us | 49 | 50 | 98.00 |
V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 4.010s | 850.102us | 50 | 50 | 100.00 |
V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 0.950s | 109.856us | 50 | 50 | 100.00 |
V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0.710s | 29.518us | 50 | 50 | 100.00 |
V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 2.210s | 702.039us | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 2.210s | 702.039us | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 2.210s | 702.039us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0.670s | 49.853us | 50 | 50 | 100.00 |
V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0.720s | 61.848us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 1.650s | 282.317us | 50 | 50 | 100.00 |
V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0.700s | 21.014us | 20 | 20 | 100.00 |
V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0.700s | 21.014us | 20 | 20 | 100.00 |
V2S | TOTAL | 374 | 375 | 99.73 | |||
V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 32.100s | 7.845ms | 49 | 50 | 98.00 |
V3 | TOTAL | 49 | 50 | 98.00 | |||
TOTAL | 1068 | 1070 | 99.81 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 12 | 12 | 12 | 100.00 |
V2S | 9 | 9 | 8 | 88.89 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.91 | 98.21 | 96.58 | 99.44 | 96.00 | 96.27 | 100.00 | 98.85 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 1 failures:
9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1085180214
Line 642, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pwrmgr_base_vseq.sv:264) [pwrmgr_aborted_low_power_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*])
has 1 failures:
36.pwrmgr_stress_all_with_rand_reset.3573209662
Line 2771, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6955806188 ps: (pwrmgr_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.pwrmgr_aborted_low_power_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (1 [0x1] vs 0 [0x0])
UVM_INFO @ 6955806188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---