864bd870c
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwrmgr_smoke | 0.740s | 29.665us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0.700s | 35.846us | 5 | 5 | 100.00 |
V1 | csr_rw | pwrmgr_csr_rw | 0.840s | 32.521us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 3.060s | 211.594us | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwrmgr_csr_aliasing | 1.040s | 40.791us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 1.200s | 86.439us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0.840s | 32.521us | 20 | 20 | 100.00 |
pwrmgr_csr_aliasing | 1.040s | 40.791us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | wakeup | pwrmgr_wakeup | 1.670s | 262.655us | 50 | 50 | 100.00 |
V2 | control_clks | pwrmgr_wakeup | 1.670s | 262.655us | 50 | 50 | 100.00 |
V2 | aborted_low_power | pwrmgr_aborted_low_power | 0.820s | 35.489us | 50 | 50 | 100.00 |
pwrmgr_lowpower_invalid | 0.800s | 40.543us | 50 | 50 | 100.00 | ||
V2 | reset | pwrmgr_reset | 1.170s | 60.133us | 50 | 50 | 100.00 |
pwrmgr_reset_invalid | 1.020s | 72.014us | 0 | 50 | 0.00 | ||
V2 | main_power_glitch_reset | pwrmgr_reset | 1.170s | 60.133us | 50 | 50 | 100.00 |
V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 1.700s | 263.466us | 50 | 50 | 100.00 |
V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 1.680s | 274.119us | 50 | 50 | 100.00 |
V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0.960s | 54.186us | 50 | 50 | 100.00 |
V2 | stress_all | pwrmgr_stress_all | 7.890s | 1.523ms | 50 | 50 | 100.00 |
V2 | intr_test | pwrmgr_intr_test | 0.740s | 24.265us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 2.900s | 175.627us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwrmgr_tl_errors | 2.900s | 175.627us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0.700s | 35.846us | 5 | 5 | 100.00 |
pwrmgr_csr_rw | 0.840s | 32.521us | 20 | 20 | 100.00 | ||
pwrmgr_csr_aliasing | 1.040s | 40.791us | 5 | 5 | 100.00 | ||
pwrmgr_same_csr_outstanding | 0.960s | 49.519us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0.700s | 35.846us | 5 | 5 | 100.00 |
pwrmgr_csr_rw | 0.840s | 32.521us | 20 | 20 | 100.00 | ||
pwrmgr_csr_aliasing | 1.040s | 40.791us | 5 | 5 | 100.00 | ||
pwrmgr_same_csr_outstanding | 0.960s | 49.519us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 490 | 540 | 90.74 | |||
V2S | tl_intg_err | pwrmgr_tl_intg_err | 1.710s | 218.543us | 20 | 20 | 100.00 |
pwrmgr_sec_cm | 1.610s | 696.421us | 5 | 5 | 100.00 | ||
V2S | prim_count_check | pwrmgr_sec_cm | 1.610s | 696.421us | 5 | 5 | 100.00 |
V2S | prim_fsm_check | pwrmgr_sec_cm | 1.610s | 696.421us | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 1.710s | 218.543us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 4.140s | 748.498us | 50 | 50 | 100.00 |
V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 3.870s | 901.239us | 50 | 50 | 100.00 |
V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 0.990s | 77.664us | 50 | 50 | 100.00 |
V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0.660s | 29.403us | 50 | 50 | 100.00 |
V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 1.610s | 696.421us | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 1.610s | 696.421us | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 1.610s | 696.421us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0.690s | 54.069us | 50 | 50 | 100.00 |
V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0.780s | 48.800us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 1.750s | 299.706us | 50 | 50 | 100.00 |
V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0.840s | 32.521us | 20 | 20 | 100.00 |
V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0.840s | 32.521us | 20 | 20 | 100.00 |
V2S | TOTAL | 375 | 375 | 100.00 | |||
V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 35.570s | 7.793ms | 50 | 50 | 100.00 |
V3 | TOTAL | 50 | 50 | 100.00 | |||
TOTAL | 1020 | 1070 | 95.33 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 12 | 12 | 11 | 91.67 |
V2S | 9 | 9 | 9 | 100.00 |
V3 | 1 | 1 | 1 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
94.80 | 98.22 | 96.58 | 99.44 | 74.00 | 96.32 | 100.00 | 99.02 |
Offending '(fast_state == FastPwrStateRomCheckGood)'
has 50 failures:
0.pwrmgr_reset_invalid.3865395960
Line 293, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest/run.log
Offending '(fast_state == FastPwrStateRomCheckGood)'
UVM_ERROR @ 75707155 ps: (pwrmgr_sec_cm_checker_assert.sv:69) [ASSERT FAILED] RomAllowCheckGoodState_A
UVM_INFO @ 75707155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_reset_invalid.3247790087
Line 246, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest/run.log
Offending '(fast_state == FastPwrStateRomCheckGood)'
UVM_ERROR @ 119410881 ps: (pwrmgr_sec_cm_checker_assert.sv:69) [ASSERT FAILED] RomAllowCheckGoodState_A
UVM_INFO @ 119410881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.