PWRMGR Simulation Results

Sunday September 17 2023 19:02:18 UTC

GitHub Revision: `3451d3b85`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 266892513

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.720s	28.749us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.680s	31.434us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.670s	24.689us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.560s	315.372us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.970s	76.354us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.420s	54.832us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.670s	24.689us	20	20	100.00
		pwrmgr_csr_aliasing	0.970s	76.354us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.480s	259.599us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.480s	259.599us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.810s	40.347us	50	50	100.00
		pwrmgr_lowpower_invalid	0.780s	40.666us	50	50	100.00
V2	reset	pwrmgr_reset	1.450s	86.595us	50	50	100.00
		pwrmgr_reset_invalid	0.980s	69.288us	0	50	0.00
V2	main_power_glitch_reset	pwrmgr_reset	1.450s	86.595us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.720s	331.679us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.560s	273.345us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.940s	69.826us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.590s	1.811ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	55.093us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.960s	151.639us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.960s	151.639us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.680s	31.434us	5	5	100.00
		pwrmgr_csr_rw	0.670s	24.689us	20	20	100.00
		pwrmgr_csr_aliasing	0.970s	76.354us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.850s	45.623us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.680s	31.434us	5	5	100.00
		pwrmgr_csr_rw	0.670s	24.689us	20	20	100.00
		pwrmgr_csr_aliasing	0.970s	76.354us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.850s	45.623us	20	20	100.00
V2		TOTAL			490	540	90.74
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.690s	281.661us	20	20	100.00
		pwrmgr_sec_cm	1.670s	822.833us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.670s	822.833us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.670s	822.833us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.690s	281.661us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.250s	890.485us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.280s	815.419us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.960s	69.574us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.710s	30.670us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.670s	822.833us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.670s	822.833us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.670s	822.833us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.660s	42.975us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	61.013us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.580s	348.370us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.670s	24.689us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.670s	24.689us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	37.640s	8.395ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1020	1070	95.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.80	98.22	96.58	99.44	74.00	96.32	100.00	99.02

Failure Buckets

Offending '(fast_state == FastPwrStateRomCheckGood)' has 50 failures:

Test pwrmgr_reset_invalid has 50 failures.

0.pwrmgr_reset_invalid.4124757748
Line 259, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest/run.log

      Offending '(fast_state == FastPwrStateRomCheckGood)'
  UVM_ERROR @ 343143107 ps: (pwrmgr_sec_cm_checker_assert.sv:69) [ASSERT FAILED] RomAllowCheckGoodState_A
  UVM_INFO @ 343143107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_reset_invalid.766103945
Line 242, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest/run.log

      Offending '(fast_state == FastPwrStateRomCheckGood)'
  UVM_ERROR @ 213893601 ps: (pwrmgr_sec_cm_checker_assert.sv:69) [ASSERT FAILED] RomAllowCheckGoodState_A
  UVM_INFO @ 213893601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.