8c6aecd4d
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwrmgr_smoke | 0.710s | 27.516us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0.680s | 24.406us | 5 | 5 | 100.00 |
V1 | csr_rw | pwrmgr_csr_rw | 0.720s | 21.735us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 2.820s | 261.190us | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwrmgr_csr_aliasing | 1.010s | 53.359us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 1.380s | 368.868us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0.720s | 21.735us | 20 | 20 | 100.00 |
pwrmgr_csr_aliasing | 1.010s | 53.359us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | wakeup | pwrmgr_wakeup | 1.510s | 237.183us | 50 | 50 | 100.00 |
V2 | control_clks | pwrmgr_wakeup | 1.510s | 237.183us | 50 | 50 | 100.00 |
V2 | aborted_low_power | pwrmgr_aborted_low_power | 0.800s | 31.790us | 50 | 50 | 100.00 |
pwrmgr_lowpower_invalid | 0.780s | 42.689us | 49 | 50 | 98.00 | ||
V2 | reset | pwrmgr_reset | 1.150s | 100.798us | 50 | 50 | 100.00 |
pwrmgr_reset_invalid | 1.100s | 112.409us | 50 | 50 | 100.00 | ||
V2 | main_power_glitch_reset | pwrmgr_reset | 1.150s | 100.798us | 50 | 50 | 100.00 |
V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 1.500s | 229.217us | 50 | 50 | 100.00 |
V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 1.400s | 248.322us | 50 | 50 | 100.00 |
V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0.970s | 58.566us | 50 | 50 | 100.00 |
V2 | stress_all | pwrmgr_stress_all | 9.060s | 2.989ms | 50 | 50 | 100.00 |
V2 | intr_test | pwrmgr_intr_test | 0.670s | 21.271us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 2.820s | 98.924us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwrmgr_tl_errors | 2.820s | 98.924us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0.680s | 24.406us | 5 | 5 | 100.00 |
pwrmgr_csr_rw | 0.720s | 21.735us | 20 | 20 | 100.00 | ||
pwrmgr_csr_aliasing | 1.010s | 53.359us | 5 | 5 | 100.00 | ||
pwrmgr_same_csr_outstanding | 0.910s | 227.468us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0.680s | 24.406us | 5 | 5 | 100.00 |
pwrmgr_csr_rw | 0.720s | 21.735us | 20 | 20 | 100.00 | ||
pwrmgr_csr_aliasing | 1.010s | 53.359us | 5 | 5 | 100.00 | ||
pwrmgr_same_csr_outstanding | 0.910s | 227.468us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 539 | 540 | 99.81 | |||
V2S | tl_intg_err | pwrmgr_tl_intg_err | 1.710s | 197.854us | 20 | 20 | 100.00 |
pwrmgr_sec_cm | 2.050s | 654.552us | 5 | 5 | 100.00 | ||
V2S | prim_count_check | pwrmgr_sec_cm | 2.050s | 654.552us | 5 | 5 | 100.00 |
V2S | prim_fsm_check | pwrmgr_sec_cm | 2.050s | 654.552us | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 1.710s | 197.854us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 4.160s | 786.653us | 50 | 50 | 100.00 |
V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 3.850s | 831.192us | 50 | 50 | 100.00 |
V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 0.970s | 114.806us | 50 | 50 | 100.00 |
V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0.690s | 29.181us | 50 | 50 | 100.00 |
V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 2.050s | 654.552us | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 2.050s | 654.552us | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 2.050s | 654.552us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0.650s | 51.633us | 50 | 50 | 100.00 |
V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0.700s | 48.351us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 1.690s | 307.587us | 50 | 50 | 100.00 |
V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0.720s | 21.735us | 20 | 20 | 100.00 |
V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0.720s | 21.735us | 20 | 20 | 100.00 |
V2S | TOTAL | 375 | 375 | 100.00 | |||
V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 44.300s | 9.210ms | 48 | 50 | 96.00 |
V3 | TOTAL | 48 | 50 | 96.00 | |||
TOTAL | 1067 | 1070 | 99.72 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 12 | 12 | 11 | 91.67 |
V2S | 9 | 9 | 9 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.90 | 98.22 | 96.44 | 99.44 | 96.00 | 96.32 | 100.00 | 98.85 |
UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
has 1 failures:
3.pwrmgr_lowpower_invalid.351337605
Line 217, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_lowpower_invalid/latest/run.log
UVM_FATAL @ 47337984 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
UVM_INFO @ 47337984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pwrmgr_base_vseq.sv:264) [pwrmgr_aborted_low_power_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*])
has 1 failures:
4.pwrmgr_stress_all_with_rand_reset.928669275
Line 8433, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7368549684 ps: (pwrmgr_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.pwrmgr_aborted_low_power_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (1 [0x1] vs 0 [0x0])
UVM_INFO @ 7368549684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]'
has 1 failures:
34.pwrmgr_stress_all_with_rand_reset.2108660626
Line 1326, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_stress_all_with_rand_reset/latest/run.log
Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]'
UVM_ERROR @ 6584394301 ps: (pwrmgr_sec_cm_checker_assert.sv:128) [ASSERT FAILED] RstreqChkMainpd_A
UVM_INFO @ 6584394301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---