PWRMGR Simulation Results

Wednesday September 27 2023 19:02:42 UTC

GitHub Revision: 38769a5e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2962962794

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	30.930us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.650s	65.559us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.680s	35.231us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.270s	558.584us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.020s	136.342us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.090s	50.288us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.680s	35.231us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	136.342us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.660s	249.838us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.660s	249.838us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.830s	39.538us	50	50	100.00
		pwrmgr_lowpower_invalid	0.790s	43.516us	50	50	100.00
V2	reset	pwrmgr_reset	1.250s	71.171us	50	50	100.00
		pwrmgr_reset_invalid	1.120s	105.850us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.250s	71.171us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.860s	317.819us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.630s	251.884us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.050s	62.857us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	10.050s	2.109ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.690s	96.028us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.480s	50.736us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.480s	50.736us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.650s	65.559us	5	5	100.00
		pwrmgr_csr_rw	0.680s	35.231us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	136.342us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	153.641us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.650s	65.559us	5	5	100.00
		pwrmgr_csr_rw	0.680s	35.231us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	136.342us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	153.641us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.640s	200.900us	20	20	100.00
		pwrmgr_sec_cm	2.200s	607.132us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.200s	607.132us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.200s	607.132us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.640s	200.900us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.990s	752.639us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.170s	799.721us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.990s	95.807us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	29.039us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.200s	607.132us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.200s	607.132us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.200s	607.132us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.690s	34.655us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.700s	49.012us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.590s	301.694us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.680s	35.231us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.680s	35.231us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	45.000s	10.716ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1068	1070	99.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.22	96.58	99.44	96.00	96.32	100.00	98.85

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 13.pwrmgr_stress_all_with_rand_reset.347278501
      Line 5456, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6628165228 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 6628165228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 35.pwrmgr_stress_all_with_rand_reset.181396347
      Line 3847, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 9122335160 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
        UVM_INFO @ 9122335160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2023.09.25_02.07.42
• 2023.09.18_00.17.56
• 2023.09.14_02.47.55
• 2023.09.11_04.18.22
• 2023.09.07_04.33.27
• 2023.09.04_02.32.59