PWRMGR Simulation Results

Sunday October 01 2023 19:02:47 UTC

GitHub Revision: 7b89440c3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3649974514

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.730s 30.311us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.660s 47.119us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.660s 31.237us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.290s 325.761us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 0.970s 45.167us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.520s 113.943us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.660s 31.237us 20 20 100.00
pwrmgr_csr_aliasing 0.970s 45.167us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.560s 272.813us 49 50 98.00
V2 control_clks pwrmgr_wakeup 1.560s 272.813us 49 50 98.00
V2 aborted_low_power pwrmgr_aborted_low_power 0.810s 47.162us 50 50 100.00
pwrmgr_lowpower_invalid 0.780s 44.343us 50 50 100.00
V2 reset pwrmgr_reset 1.190s 63.282us 50 50 100.00
pwrmgr_reset_invalid 1.090s 102.223us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.190s 63.282us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.510s 274.185us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.650s 274.558us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.950s 60.706us 50 50 100.00
V2 stress_all pwrmgr_stress_all 8.990s 1.864ms 49 50 98.00
V2 intr_test pwrmgr_intr_test 0.690s 20.566us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.600s 551.551us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.600s 551.551us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.660s 47.119us 5 5 100.00
pwrmgr_csr_rw 0.660s 31.237us 20 20 100.00
pwrmgr_csr_aliasing 0.970s 45.167us 5 5 100.00
pwrmgr_same_csr_outstanding 0.940s 52.481us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.660s 47.119us 5 5 100.00
pwrmgr_csr_rw 0.660s 31.237us 20 20 100.00
pwrmgr_csr_aliasing 0.970s 45.167us 5 5 100.00
pwrmgr_same_csr_outstanding 0.940s 52.481us 20 20 100.00
V2 TOTAL 538 540 99.63
V2S tl_intg_err pwrmgr_tl_intg_err 1.780s 237.557us 20 20 100.00
pwrmgr_sec_cm 2.080s 629.479us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.080s 629.479us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.080s 629.479us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.780s 237.557us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 4.050s 809.256us 49 50 98.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 4.450s 843.114us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 0.970s 75.886us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.710s 29.525us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.080s 629.479us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.080s 629.479us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.080s 629.479us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.680s 37.960us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.700s 54.750us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.640s 276.334us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.660s 31.237us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.660s 31.237us 20 20 100.00
V2S TOTAL 374 375 99.73
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 39.410s 11.120ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1067 1070 99.72

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 10 83.33
V2S 9 9 8 88.89
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.94 98.22 96.58 99.44 96.00 96.32 100.00 99.02

Failure Buckets

Past Results