PWRMGR Simulation Results

Wednesday October 04 2023 19:02:35 UTC

GitHub Revision: 1522c8119

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1107990535

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.810s	25.542us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.660s	37.872us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.690s	24.253us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.620s	318.761us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.970s	73.468us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.130s	63.654us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.690s	24.253us	20	20	100.00
		pwrmgr_csr_aliasing	0.970s	73.468us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.420s	255.162us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.420s	255.162us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.840s	109.694us	50	50	100.00
		pwrmgr_lowpower_invalid	0.760s	48.202us	49	50	98.00
V2	reset	pwrmgr_reset	1.450s	88.260us	50	50	100.00
		pwrmgr_reset_invalid	1.100s	109.400us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.450s	88.260us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.610s	294.971us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.580s	251.076us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.970s	63.906us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	9.380s	1.850ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.670s	34.487us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.740s	510.801us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.740s	510.801us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.660s	37.872us	5	5	100.00
		pwrmgr_csr_rw	0.690s	24.253us	20	20	100.00
		pwrmgr_csr_aliasing	0.970s	73.468us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	49.922us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.660s	37.872us	5	5	100.00
		pwrmgr_csr_rw	0.690s	24.253us	20	20	100.00
		pwrmgr_csr_aliasing	0.970s	73.468us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	49.922us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.620s	210.177us	20	20	100.00
		pwrmgr_sec_cm	2.030s	617.105us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.030s	617.105us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.030s	617.105us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.620s	210.177us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.120s	860.420us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.300s	898.123us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.960s	78.469us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.670s	30.287us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.030s	617.105us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.030s	617.105us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.030s	617.105us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.740s	78.705us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.770s	60.827us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.670s	318.604us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.690s	24.253us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.690s	24.253us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	50.860s	10.819ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1069	1070	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.94	98.22	96.58	99.44	96.00	96.32	100.00	99.02

Failure Buckets

• UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough has 1 failures:
  • Test pwrmgr_lowpower_invalid has 1 failures.

    • 32.pwrmgr_lowpower_invalid.3852216078
      Line 205, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_lowpower_invalid/latest/run.log

        UVM_FATAL @  36141111 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
        UVM_INFO @  36141111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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