ROM_CTRL Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3641199223

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	33.830s	15.316ms	48	50	96.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.320s	2.310ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	13.640s	2.091ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	11.370s	7.216ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.250s	8.241ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.960s	22.539ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	13.640s	2.091ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.250s	8.241ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	11.280s	1.504ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.440s	6.880ms	5	5	100.00
V1		TOTAL			113	115	98.26
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	15.810s	12.428ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.664m	60.286ms	48	50	96.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	28.600s	4.153ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	15.010s	8.895ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.110s	5.296ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.110s	5.296ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.320s	2.310ms	5	5	100.00
		rom_ctrl_csr_rw	13.640s	2.091ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.250s	8.241ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.670s	8.552ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.320s	2.310ms	5	5	100.00
		rom_ctrl_csr_rw	13.640s	2.091ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.250s	8.241ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.670s	8.552ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	5.269m	40.111ms	48	50	96.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	5.067m	63.017ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.697m	2.174ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.189m	7.982ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.697m	2.174ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	5.269m	40.111ms	48	50	96.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	5.269m	40.111ms	48	50	96.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	5.269m	40.111ms	48	50	96.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	5.269m	40.111ms	48	50	96.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	5.269m	40.111ms	48	50	96.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.697m	2.174ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.697m	2.174ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	33.830s	15.316ms	48	50	96.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	33.830s	15.316ms	48	50	96.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	33.830s	15.316ms	48	50	96.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.189m	7.982ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	5.269m	40.111ms	48	50	96.00
		rom_ctrl_kmac_err_chk	28.600s	4.153ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	5.269m	40.111ms	48	50	96.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	5.269m	40.111ms	48	50	96.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	5.269m	40.111ms	48	50	96.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	5.067m	63.017ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.697m	2.174ms	5	5	100.00
V2S		TOTAL			93	95	97.89
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.849h	326.172ms	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			478	500	95.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.76	97.16	93.27	97.88	86.67	99.01	98.19	98.14

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 12 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.1817036580
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:eb30f0a2-f409-4f86-9338-bf4f7e7f22be
```
  - 3.rom_ctrl_stress_all_with_rand_reset.3296678081
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:fbf9d1de-893c-478b-8477-9d8a60bb403f
```
  - ... and 10 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 8 failures:

Test rom_ctrl_stress_all_with_rand_reset has 4 failures.

6.rom_ctrl_stress_all_with_rand_reset.3966943725
Line 225, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10265927144 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x18e72bce
  UVM_INFO @ 10265927144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.rom_ctrl_stress_all_with_rand_reset.3407749236
Line 228, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 14903319870 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x56889fe6
  UVM_INFO @ 14903319870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test rom_ctrl_smoke has 2 failures.

7.rom_ctrl_smoke.3036456075
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/7.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10012569446 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xbe59cc1e
  UVM_INFO @ 10012569446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.rom_ctrl_smoke.4112670712
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/41.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10009906794 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x3ab93958
  UVM_INFO @ 10009906794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_ctrl_stress_all has 2 failures.

12.rom_ctrl_stress_all.3445155812
Line 220, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10140014059 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x4d30bd84
  UVM_INFO @ 10140014059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.rom_ctrl_stress_all.3965094259
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/46.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10019231020 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x7bc2f9e8
  UVM_INFO @ 10019231020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 26.rom_ctrl_corrupt_sig_fatal_chk.295942848
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 29545507409 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 29545507409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 34.rom_ctrl_corrupt_sig_fatal_chk.1744105007
    Line 249, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```