042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 39.500s | 15.765ms | 34 | 50 | 68.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 15.380s | 3.445ms | 4 | 5 | 80.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 16.390s | 4.210ms | 15 | 20 | 75.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 15.060s | 3.855ms | 4 | 5 | 80.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 12.800s | 7.512ms | 3 | 5 | 60.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 16.320s | 11.442ms | 18 | 20 | 90.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 16.390s | 4.210ms | 15 | 20 | 75.00 |
| rom_ctrl_csr_aliasing | 12.800s | 7.512ms | 3 | 5 | 60.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 12.760s | 11.885ms | 4 | 5 | 80.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 12.660s | 2.851ms | 4 | 5 | 80.00 |
| V1 | TOTAL | 86 | 115 | 74.78 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 17.700s | 12.563ms | 36 | 50 | 72.00 |
| V2 | stress_all | rom_ctrl_stress_all | 1.615m | 38.039ms | 32 | 50 | 64.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 33.730s | 20.326ms | 40 | 50 | 80.00 |
| V2 | alert_test | rom_ctrl_alert_test | 16.150s | 8.580ms | 34 | 50 | 68.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 20.600s | 2.091ms | 12 | 20 | 60.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 20.600s | 2.091ms | 12 | 20 | 60.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 15.380s | 3.445ms | 4 | 5 | 80.00 |
| rom_ctrl_csr_rw | 16.390s | 4.210ms | 15 | 20 | 75.00 | ||
| rom_ctrl_csr_aliasing | 12.800s | 7.512ms | 3 | 5 | 60.00 | ||
| rom_ctrl_same_csr_outstanding | 16.360s | 7.376ms | 17 | 20 | 85.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 15.380s | 3.445ms | 4 | 5 | 80.00 |
| rom_ctrl_csr_rw | 16.390s | 4.210ms | 15 | 20 | 75.00 | ||
| rom_ctrl_csr_aliasing | 12.800s | 7.512ms | 3 | 5 | 60.00 | ||
| rom_ctrl_same_csr_outstanding | 16.360s | 7.376ms | 17 | 20 | 85.00 | ||
| V2 | TOTAL | 171 | 240 | 71.25 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 10.066m | 116.867ms | 35 | 50 | 70.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 6.265m | 55.625ms | 14 | 20 | 70.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 2.041m | 3.878ms | 4 | 5 | 80.00 |
| rom_ctrl_tl_intg_err | 1.422m | 8.706ms | 16 | 20 | 80.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 2.041m | 3.878ms | 4 | 5 | 80.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 10.066m | 116.867ms | 35 | 50 | 70.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 10.066m | 116.867ms | 35 | 50 | 70.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 10.066m | 116.867ms | 35 | 50 | 70.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 10.066m | 116.867ms | 35 | 50 | 70.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 10.066m | 116.867ms | 35 | 50 | 70.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 2.041m | 3.878ms | 4 | 5 | 80.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 2.041m | 3.878ms | 4 | 5 | 80.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 39.500s | 15.765ms | 34 | 50 | 68.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 39.500s | 15.765ms | 34 | 50 | 68.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 39.500s | 15.765ms | 34 | 50 | 68.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.422m | 8.706ms | 16 | 20 | 80.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 10.066m | 116.867ms | 35 | 50 | 70.00 |
| rom_ctrl_kmac_err_chk | 33.730s | 20.326ms | 40 | 50 | 80.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 10.066m | 116.867ms | 35 | 50 | 70.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 10.066m | 116.867ms | 35 | 50 | 70.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 10.066m | 116.867ms | 35 | 50 | 70.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 6.265m | 55.625ms | 14 | 20 | 70.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 2.041m | 3.878ms | 4 | 5 | 80.00 |
| V2S | TOTAL | 69 | 95 | 72.63 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.913h | 57.566ms | 21 | 50 | 42.00 |
| V3 | TOTAL | 21 | 50 | 42.00 | |||
| TOTAL | 347 | 500 | 69.40 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 0 | 0.00 |
| V2 | 6 | 6 | 0 | 0.00 |
| V2S | 4 | 4 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.49 | 97.11 | 92.68 | 97.88 | 100.00 | 98.37 | 98.04 | 98.38 |
Exit reason: Error: User command failed Job returned non-zero exit code has 119 failures:
Test rom_ctrl_sec_cm has 1 failures.
0.rom_ctrl_sec_cm.236399953512637746142933612060426249302955588738310472758180404802522703028
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log
[make]: simulate
cd /workspace/0.rom_ctrl_sec_cm/latest && /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691791028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.691791028
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:30 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test rom_ctrl_mem_walk has 1 failures.
0.rom_ctrl_mem_walk.10388327615962279682745361288549247576894292269057343812869318051113069759107
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_mem_walk/latest/run.log
[make]: simulate
cd /workspace/0.rom_ctrl_mem_walk/latest && /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474611843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.1474611843
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:31 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test rom_ctrl_mem_partial_access has 1 failures.
0.rom_ctrl_mem_partial_access.45604584784246382892228757026495391236398016985498225025880819143028973328078
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_mem_partial_access/latest/run.log
[make]: simulate
cd /workspace/0.rom_ctrl_mem_partial_access/latest && /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834730190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.3834730190
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:29 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test rom_ctrl_stress_all has 15 failures.
1.rom_ctrl_stress_all.21001790059030245958850947795133470172742945031478790565906119479798616745041
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all/latest/run.log
[make]: simulate
cd /workspace/1.rom_ctrl_stress_all/latest && /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016759889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.4016759889
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:30 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
2.rom_ctrl_stress_all.93465754402462258107476882188573918502871081866291413938983525139998347153515
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all/latest/run.log
[make]: simulate
cd /workspace/2.rom_ctrl_stress_all/latest && /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058066539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.1058066539
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:31 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 13 more failures.
Test rom_ctrl_max_throughput_chk has 13 failures.
1.rom_ctrl_max_throughput_chk.85542718391275401390778527984406203436615442592928566582920424342719695821775
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_max_throughput_chk/latest/run.log
[make]: simulate
cd /workspace/1.rom_ctrl_max_throughput_chk/latest && /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865999823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.865999823
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:29 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
3.rom_ctrl_max_throughput_chk.73709941536105649947643089377695425515045894249075954947499996802732173475658
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_max_throughput_chk/latest/run.log
[make]: simulate
cd /workspace/3.rom_ctrl_max_throughput_chk/latest && /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189948234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3189948234
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:30 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 11 more failures.
... and 14 more tests.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 25 failures:
Test rom_ctrl_stress_all_with_rand_reset has 14 failures.
0.rom_ctrl_stress_all_with_rand_reset.38462600062535163283592908497166352913410748044645542348232783961147779568673
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:3bda5e4c-ea09-435a-b8d7-63cfbd055d66
1.rom_ctrl_stress_all_with_rand_reset.84869450794143038593416971301713772045816444362832728864138035496355179416979
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:9f50c661-da16-42f7-9944-fea7fe5d5031
... and 12 more failures.
Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.
2.rom_ctrl_corrupt_sig_fatal_chk.78401066117253676506636724791511279954989400721748629514580267539192145429571
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
Job ID: smart:83eb8384-3a83-4185-825b-2b2117dd24ef
25.rom_ctrl_corrupt_sig_fatal_chk.29904468178883079831170141500257682328453762978759596090131319865999712191816
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
Job ID: smart:8b979f10-473f-4af8-86bf-b6dff4f257b7
Test rom_ctrl_stress_all has 3 failures.
28.rom_ctrl_stress_all.75446369158440912290743175126170326528960691740289991599682204300797452619025
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/28.rom_ctrl_stress_all/latest/run.log
Job ID: smart:6a7d65d8-c3b9-4356-93c3-aa72488befc0
31.rom_ctrl_stress_all.6664733468112034903119129968538989698967445175416776643901164897712283442413
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/31.rom_ctrl_stress_all/latest/run.log
Job ID: smart:c90ee7a6-6fef-4edd-82c5-7397a7ec90c1
... and 1 more failures.
Test rom_ctrl_alert_test has 2 failures.
36.rom_ctrl_alert_test.79547933573839183353053347158016162436690826594393882969646966362108022393846
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/36.rom_ctrl_alert_test/latest/run.log
Job ID: smart:9463b403-8916-4b1a-ab1e-42f15fb41652
45.rom_ctrl_alert_test.75025301877649292552238148510049213404870062199505955160099651319918189140278
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/45.rom_ctrl_alert_test/latest/run.log
Job ID: smart:a217aaac-f7c7-4b94-86fc-6ebea70ea7ca
Test rom_ctrl_max_throughput_chk has 1 failures.
37.rom_ctrl_max_throughput_chk.5846255742462375526812775516614980026254284776070007251493449340961687169496
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/37.rom_ctrl_max_throughput_chk/latest/run.log
Job ID: smart:4aabfb2e-c63c-4941-9ede-6e42485bf70f
... and 2 more tests.
Job rom_ctrl-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
Test rom_ctrl_tl_errors has 1 failures.
0.rom_ctrl_tl_errors.5088441108472962381196746622010956646067767882594961138347598216202354479607
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_tl_errors/latest/run.log
Job ID: smart:31da3a7c-f6f5-4493-b5e4-bbba67edf009
Test rom_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
0.rom_ctrl_csr_mem_rw_with_rand_reset.25443057966463701264828562518130972301632383968693616756926964660247939997907
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
Job ID: smart:4dd64725-124f-4eb4-83e4-d17dd255bdaf
Test rom_ctrl_tl_intg_err has 2 failures.
2.rom_ctrl_tl_intg_err.39385101408184026116903227356488653444451264325908412965711422052334097824296
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_tl_intg_err/latest/run.log
Job ID: smart:31993bdb-45f5-4dd9-a631-0c00f6a3f671
6.rom_ctrl_tl_intg_err.26635444000978440808939126949364850177273127660691122546923643852568748124278
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/6.rom_ctrl_tl_intg_err/latest/run.log
Job ID: smart:200bb23d-784d-47eb-92e7-fa6c806a07a9
Test rom_ctrl_csr_rw has 1 failures.
5.rom_ctrl_csr_rw.109397484122116285914820696792953397965086318121440071688884358741568029605603
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_csr_rw/latest/run.log
Job ID: smart:ba186ee9-41c6-47cf-a90c-05f1abb0920a
Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
15.rom_ctrl_passthru_mem_tl_intg_err.99413119114623149317542619563601103617762925331808419452930402612392946286710
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
Job ID: smart:69ee8cae-88eb-46cc-8853-d7f7f281188b
UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:
Test rom_ctrl_passthru_mem_tl_intg_err has 2 failures.
6.rom_ctrl_passthru_mem_tl_intg_err.37508104055344002013237141191750133026503769364316548853617400757583017535199
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 10013423034 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x35af800c
UVM_INFO @ 10013423034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.rom_ctrl_passthru_mem_tl_intg_err.19881761902274682054706456951413249227427229795732623390410684309945274549383
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 10012641533 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xbf6a0004
UVM_INFO @ 10012641533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
42.rom_ctrl_stress_all_with_rand_reset.104030034427136025320489807199377065813386821938336489902400325816081548379461
Line 274, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 19244383602 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3748ef8b
UVM_INFO @ 19244383602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---