cf38c1d296| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 41.280s | 19.083ms | 47 | 50 | 94.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 19.570s | 2.017ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 16.670s | 2.051ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 14.520s | 3.275ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 16.010s | 7.517ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 16.300s | 8.126ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 16.670s | 2.051ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 16.010s | 7.517ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 11.830s | 5.148ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 16.450s | 5.286ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 112 | 115 | 97.39 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 17.310s | 7.909ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 1.808m | 12.948ms | 48 | 50 | 96.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 34.470s | 8.168ms | 49 | 50 | 98.00 |
| V2 | alert_test | rom_ctrl_alert_test | 17.300s | 8.419ms | 49 | 50 | 98.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 18.380s | 1.589ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 18.380s | 1.589ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 19.570s | 2.017ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 16.670s | 2.051ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 16.010s | 7.517ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 18.140s | 9.299ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 19.570s | 2.017ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 16.670s | 2.051ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 16.010s | 7.517ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 18.140s | 9.299ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 236 | 240 | 98.33 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 9.296m | 116.343ms | 48 | 50 | 96.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 5.520m | 152.084ms | 19 | 20 | 95.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 1.897m | 2.858ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 1.465m | 2.445ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.897m | 2.858ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.296m | 116.343ms | 48 | 50 | 96.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.296m | 116.343ms | 48 | 50 | 96.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 9.296m | 116.343ms | 48 | 50 | 96.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.296m | 116.343ms | 48 | 50 | 96.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.296m | 116.343ms | 48 | 50 | 96.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.897m | 2.858ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.897m | 2.858ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 41.280s | 19.083ms | 47 | 50 | 94.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 41.280s | 19.083ms | 47 | 50 | 94.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 41.280s | 19.083ms | 47 | 50 | 94.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.465m | 2.445ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 9.296m | 116.343ms | 48 | 50 | 96.00 |
| rom_ctrl_kmac_err_chk | 34.470s | 8.168ms | 49 | 50 | 98.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 9.296m | 116.343ms | 48 | 50 | 96.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.296m | 116.343ms | 48 | 50 | 96.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 9.296m | 116.343ms | 48 | 50 | 96.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 5.520m | 152.084ms | 19 | 20 | 95.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.897m | 2.858ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 92 | 95 | 96.84 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.571h | 51.188ms | 36 | 50 | 72.00 |
| V3 | TOTAL | 36 | 50 | 72.00 | |||
| TOTAL | 476 | 500 | 95.20 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 6 | 6 | 3 | 50.00 |
| V2S | 4 | 4 | 2 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.67 | 97.11 | 93.12 | 97.88 | 100.00 | 98.69 | 98.04 | 98.84 |
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
3.rom_ctrl_stress_all_with_rand_reset.6928076801905118229838025907235715229813080642459875064789054430755292165922
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:35deeb55-6895-48cc-b432-73b4b9923619
9.rom_ctrl_stress_all_with_rand_reset.48317527855619753335104340806363377518641279849978790273291767782476456089008
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:84f4e4a8-a5a9-41ca-a505-06f89539f954
... and 9 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 9 failures:
Test rom_ctrl_stress_all has 2 failures.
0.rom_ctrl_stress_all.13968288107037964170429019935225917657055358836044752262773575506062596233872
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all/latest/run.log
[make]: simulate
cd /workspace/0.rom_ctrl_stress_all/latest && /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332782224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.332782224
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:04 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
27.rom_ctrl_stress_all.56071797089568082399454873062875344864312301566197046577340836836217612336046
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/27.rom_ctrl_stress_all/latest/run.log
[make]: simulate
cd /workspace/27.rom_ctrl_stress_all/latest && /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996604846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.996604846
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:04 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test rom_ctrl_kmac_err_chk has 1 failures.
14.rom_ctrl_kmac_err_chk.34197899005484426609392962101019685625005777173981153613319171904192318324762
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/14.rom_ctrl_kmac_err_chk/latest/run.log
[make]: simulate
cd /workspace/14.rom_ctrl_kmac_err_chk/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930374170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3930374170
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:04 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test rom_ctrl_smoke has 3 failures.
16.rom_ctrl_smoke.58292561312071970392744166636840447891067168564124919695348577170217104225065
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/16.rom_ctrl_smoke/latest/run.log
[make]: simulate
cd /workspace/16.rom_ctrl_smoke/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824437033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1824437033
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:04 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
37.rom_ctrl_smoke.36344652626633990552877582709858888667848381216893058919540947246870102602478
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/37.rom_ctrl_smoke/latest/run.log
[make]: simulate
cd /workspace/37.rom_ctrl_smoke/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153837294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2153837294
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:05 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
Test rom_ctrl_alert_test has 1 failures.
20.rom_ctrl_alert_test.54158256212547764775010572500889865131314771522130220826953322504692812921036
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/20.rom_ctrl_alert_test/latest/run.log
[make]: simulate
cd /workspace/20.rom_ctrl_alert_test/latest && /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426503884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1426503884
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:04 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
23.rom_ctrl_stress_all_with_rand_reset.14876464931651013549091234115731478884444078439155839369554439705689831254552
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest && /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391367704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3391367704
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:04 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more tests.
UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:
Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
8.rom_ctrl_passthru_mem_tl_intg_err.93927554289395287795573257567374044058947907600876787775618082957641933931368
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 10005349440 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x32f60008
UVM_INFO @ 10005349440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
10.rom_ctrl_stress_all_with_rand_reset.90943493500046747482443076273065993666922260242568141592932303613054312859364
Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11420242993 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xe45e3e31
UVM_INFO @ 11420242993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.rom_ctrl_stress_all_with_rand_reset.91640565192933663274735500928371496325163236558338777771013547259895549869375
Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11280212926 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x5a120588
UVM_INFO @ 11280212926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:595) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 1 failures:
9.rom_ctrl_corrupt_sig_fatal_chk.11921930609994312738279943695412282947900949774134080784218784125978408326077
Line 266, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 4842388767 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
UVM_INFO @ 4842388767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---