ROM_CTRL Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: 5f48fbc0e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	40.320s	3.606ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.820s	1.867ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	17.020s	8.783ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.430s	16.284ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.310s	3.838ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.600s	2.115ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	17.020s	8.783ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.310s	3.838ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	16.480s	4.376ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.570s	5.397ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.270s	8.407ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.346m	23.702ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.290s	18.757ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.300s	2.165ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.560s	30.782ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.560s	30.782ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.820s	1.867ms	5	5	100.00
		rom_ctrl_csr_rw	17.020s	8.783ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.310s	3.838ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.330s	3.681ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.820s	1.867ms	5	5	100.00
		rom_ctrl_csr_rw	17.020s	8.783ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.310s	3.838ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.330s	3.681ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	10.985m	262.941ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	5.068m	31.491ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.909m	189.216us	5	5	100.00
		rom_ctrl_tl_intg_err	1.474m	2.669ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.909m	189.216us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.985m	262.941ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.985m	262.941ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.985m	262.941ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.985m	262.941ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.985m	262.941ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.909m	189.216us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.909m	189.216us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	40.320s	3.606ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	40.320s	3.606ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	40.320s	3.606ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.474m	2.669ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.985m	262.941ms	49	50	98.00
		rom_ctrl_kmac_err_chk	35.290s	18.757ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	10.985m	262.941ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.985m	262.941ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	10.985m	262.941ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	5.068m	31.491ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.909m	189.216us	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.028h	47.875ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			481	500	96.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.53	97.11	92.83	97.88	100.00	98.69	98.04	98.14

Failure Buckets

• Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 13 failures.

    • 2.rom_ctrl_stress_all_with_rand_reset.73521178050922073614825799484214465808332737538081791183276102015812107227404
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:6ea3339a-67e6-4ea9-8527-6c91cf1fc5dd
      

    • 5.rom_ctrl_stress_all_with_rand_reset.1350329289573150506730510253232052409616962685884772540660220934808834260949
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:96b928e9-dd95-49af-a9ce-1ac54bb825bf
      

    • ... and 11 more failures.

• UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 3 failures.

    • 4.rom_ctrl_stress_all_with_rand_reset.51359764367553501517317758316954677905710738514765790374704362929903489273281
      Line 272, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 24850786235 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x52283648
        UVM_INFO @ 24850786235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.rom_ctrl_stress_all_with_rand_reset.86986533272353318605562045146222989036184635832172945304381711052618203191705
      Line 284, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 23203410712 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x55d8b0eb
        UVM_INFO @ 23203410712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:

  • Test rom_ctrl_stress_all has 1 failures.

    • 19.rom_ctrl_stress_all.25283744547292360389320527061982706392426613712961996305486424214649874499288
      Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/19.rom_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 3886773558 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 3886773558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.rom_ctrl_stress_all_with_rand_reset.11210074887140331937554945688322168846338264963556943358136173823227084644603
      Line 699, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 871310824650 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 871310824650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:595) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 36.rom_ctrl_corrupt_sig_fatal_chk.4846430321421199703924507656767513629956917625546208424431780098697538107730
      Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 1809469902 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
        UVM_INFO @ 1809469902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.01.11_03.16.35
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• 2024.01.04_01.27.44
• 2024.01.01_00.55.07
• 2023.12.28_03.28.50
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