ROM_CTRL Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: 4d88b9516c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	41.740s	17.785ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.550s	8.132ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.880s	4.178ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.890s	3.952ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.470s	2.170ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.490s	8.576ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.880s	4.178ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.470s	2.170ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.990s	7.945ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.720s	4.204ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.200s	4.377ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.424m	69.459ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.400s	3.986ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.700s	2.122ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.850s	10.494ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.850s	10.494ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.550s	8.132ms	5	5	100.00
		rom_ctrl_csr_rw	16.880s	4.178ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.470s	2.170ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.200s	2.016ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.550s	8.132ms	5	5	100.00
		rom_ctrl_csr_rw	16.880s	4.178ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.470s	2.170ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.200s	2.016ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.107m	419.239ms	48	50	96.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	5.906m	68.373ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.884m	476.944us	5	5	100.00
		rom_ctrl_tl_intg_err	1.411m	10.871ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.884m	476.944us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.107m	419.239ms	48	50	96.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.107m	419.239ms	48	50	96.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.107m	419.239ms	48	50	96.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.107m	419.239ms	48	50	96.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.107m	419.239ms	48	50	96.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.884m	476.944us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.884m	476.944us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	41.740s	17.785ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	41.740s	17.785ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	41.740s	17.785ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.411m	10.871ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.107m	419.239ms	48	50	96.00
		rom_ctrl_kmac_err_chk	34.400s	3.986ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.107m	419.239ms	48	50	96.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.107m	419.239ms	48	50	96.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.107m	419.239ms	48	50	96.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	5.906m	68.373ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.884m	476.944us	5	5	100.00
V2S		TOTAL			93	95	97.89
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.916h	134.468ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			481	500	96.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.57	97.11	92.68	97.88	100.00	98.37	97.89	99.07

Failure Buckets

• Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 15 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.45879905433693473609559238450852582689729753693206747579539499252674454276872
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:677ce8d4-ff5a-4682-b096-ac59c44969a2
      

    • 3.rom_ctrl_stress_all_with_rand_reset.55674882896644585087340796487376439920978816489290537798822960860984081877480
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:9e56d46c-c6f4-4898-80b0-82de176c4f4a
      

    • ... and 13 more failures.

• UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 8.rom_ctrl_stress_all_with_rand_reset.15471334540104470284962677845009560368486435950859514389676533567696813844928
      Line 713, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 821491241234 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 821491241234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 37.rom_ctrl_corrupt_sig_fatal_chk.11590965643366333193761614523763395943233953527406943188112013661840574612708
      Line 294, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 28614967670 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 28614967670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 6.rom_ctrl_stress_all_with_rand_reset.99650086941064082771088595641273674283111509409062930785337946221990815083448
      Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 11544590429 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xa88221b5
        UVM_INFO @ 11544590429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:595) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 12.rom_ctrl_corrupt_sig_fatal_chk.3231858645076026907939196203199839958889929429489848925744018357647906152232
      Line 263, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 655039232 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
        UVM_INFO @ 655039232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.01.15_04.02.44
• 2024.01.11_03.16.35
• 2024.01.08_03.03.22
• 2024.01.04_01.27.44
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• 2023.12.28_03.28.50