ROM_CTRL Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: `796f9fb805`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	48.920s	17.706ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.010s	3.844ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.960s	7.231ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.780s	334.709us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.940s	3.992ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.820s	4.692ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.960s	7.231ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.940s	3.992ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	13.770s	6.982ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	16.420s	7.444ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.340s	8.081ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.109m	49.470ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.040s	15.426ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.670s	2.035ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.830s	4.213ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.830s	4.213ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.010s	3.844ms	5	5	100.00
		rom_ctrl_csr_rw	15.960s	7.231ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.940s	3.992ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.870s	4.084ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.010s	3.844ms	5	5	100.00
		rom_ctrl_csr_rw	15.960s	7.231ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.940s	3.992ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.870s	4.084ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.881m	112.266ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	6.996m	41.379ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.662m	203.702us	5	5	100.00
		rom_ctrl_tl_intg_err	1.350m	2.383ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.662m	203.702us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.881m	112.266ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.881m	112.266ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.881m	112.266ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.881m	112.266ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.881m	112.266ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.662m	203.702us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.662m	203.702us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	48.920s	17.706ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	48.920s	17.706ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	48.920s	17.706ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.350m	2.383ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.881m	112.266ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.040s	15.426ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.881m	112.266ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.881m	112.266ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.881m	112.266ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	6.996m	41.379ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.662m	203.702us	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.915h	342.357ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			482	500	96.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.55	97.04	92.80	97.88	100.00	98.69	98.04	98.38

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 13 failures.
  - 13.rom_ctrl_stress_all_with_rand_reset.3382431838479666358948025701984128299995163839513638357067845397759943745252
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c757e888-430f-4399-b3fc-1e298fc0aa5b
```
  - 19.rom_ctrl_stress_all_with_rand_reset.71665743428499390572246907598969534469005558493572377822717799463193658125389
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:61749dfc-b59e-4544-b95f-6d9c13959618
```
  - ... and 11 more failures.
UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 6.rom_ctrl_stress_all_with_rand_reset.3569753537545988898755837471903352337997403700105754911835774634491354321146
    Line 287, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 14475897057 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xb71b57e0
  UVM_INFO @ 14475897057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.rom_ctrl_stress_all_with_rand_reset.97486480581850221623996459517394974970075524239585035179700676514883262250414
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12134396489 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x261dfb75
  UVM_INFO @ 12134396489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 15.rom_ctrl_passthru_mem_tl_intg_err.51829227688987394749756695656874157091002332660110160649744054035811927987692
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 10007318452 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x92e80008
  UVM_INFO @ 10007318452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 45.rom_ctrl_stress_all_with_rand_reset.16404024595438592662926717656217605677921451806301509089131579905523607372635
    Line 613, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 609394746772 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 609394746772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: 796f9fb805

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `796f9fb805`