ROM_CTRL Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: 17d5a97c3b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	43.960s	4.121ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.160s	1.304ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.220s	8.378ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.880s	2.086ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.980s	9.605ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.950s	4.279ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.220s	8.378ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.980s	9.605ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	10.810s	4.276ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	16.310s	8.806ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.560s	4.213ms	49	50	98.00
V2	stress_all	rom_ctrl_stress_all	2.694m	52.194ms	47	50	94.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.300s	30.165ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	17.460s	12.524ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.370s	2.909ms	18	20	90.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.370s	2.909ms	18	20	90.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.160s	1.304ms	5	5	100.00
		rom_ctrl_csr_rw	16.220s	8.378ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.980s	9.605ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.490s	1.783ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.160s	1.304ms	5	5	100.00
		rom_ctrl_csr_rw	16.220s	8.378ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.980s	9.605ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.490s	1.783ms	20	20	100.00
V2		TOTAL			233	240	97.08
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.763m	90.312ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	5.361m	77.848ms	18	20	90.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.863m	23.600ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.357m	2.400ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.863m	23.600ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.763m	90.312ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.763m	90.312ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.763m	90.312ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.763m	90.312ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.763m	90.312ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.863m	23.600ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.863m	23.600ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	43.960s	4.121ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	43.960s	4.121ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	43.960s	4.121ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.357m	2.400ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.763m	90.312ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.300s	30.165ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.763m	90.312ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.763m	90.312ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.763m	90.312ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	5.361m	77.848ms	18	20	90.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.863m	23.600ms	5	5	100.00
V2S		TOTAL			93	95	97.89
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.652h	200.035ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			473	500	94.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	2	33.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.59	97.04	92.65	97.88	100.00	98.37	97.89	99.30

Failure Buckets

• Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 16 failures.

    • 2.rom_ctrl_stress_all_with_rand_reset.44351681275363544626193959862015827967151007945349647479857336826990079032928
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:cd40fcb2-f30a-4fcf-a576-4b6f7bc6e7e9
      

    • 3.rom_ctrl_stress_all_with_rand_reset.23827444992050018254903904055236083201809130803046650180757613793602911426016
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:1025242e-7ad4-4dc1-bbd0-09675a2a56e4
      

    • ... and 14 more failures.

• UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:

  • Test rom_ctrl_passthru_mem_tl_intg_err has 2 failures.

    • 3.rom_ctrl_passthru_mem_tl_intg_err.10613223840634943022651636098936575400168394122104854257361682035915922919141
      Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @ 10009721061 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xd2720004
        UVM_INFO @ 10009721061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.rom_ctrl_passthru_mem_tl_intg_err.38869071096473218636678410256844308758966051818430844867895117963152514393297
      Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @ 10020277178 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xbe940008
        UVM_INFO @ 10020277178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 12.rom_ctrl_stress_all_with_rand_reset.68616891301042078647283004276967259198756333159194986838595475822291640855574
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10027205796 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x54f33edc
        UVM_INFO @ 10027205796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 3 failures:

  • Test rom_ctrl_kmac_err_chk has 1 failures.

    • 25.rom_ctrl_kmac_err_chk.105378975894768573638586740758630097762619926953946533170785577248292294736464
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/25.rom_ctrl_kmac_err_chk/latest/run.log

        Job ID: smart:5004ab60-e163-4e88-9ed0-fda6bde3b100
      

  • Test rom_ctrl_max_throughput_chk has 1 failures.

    • 35.rom_ctrl_max_throughput_chk.33851260165674696445407801256444350933526593758870115863122551785433532257280
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/35.rom_ctrl_max_throughput_chk/latest/run.log

        Job ID: smart:01b5d661-9ba7-4ca0-9652-5ea57adcee25
      

  • Test rom_ctrl_stress_all has 1 failures.

    • 43.rom_ctrl_stress_all.112718629801790797376723116603241726507700539831182877825655499861882904177374
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/43.rom_ctrl_stress_all/latest/run.log

        Job ID: smart:19f3c6ba-5efb-4e6d-9880-a34d1447a0a1
      

• Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 2 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 6.rom_ctrl_stress_all_with_rand_reset.80458818901912450063496781254877484628397774863332151660111220272751047436324
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:e1b47b96-fe13-4de9-b291-df2baa1580ef
      

  • Test rom_ctrl_stress_all has 1 failures.

    • 34.rom_ctrl_stress_all.76668249830492755839752200837142705629689674391186403425532984583653420261107
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/34.rom_ctrl_stress_all/latest/run.log

        Job ID: smart:1e36102f-183a-4362-8134-ab681a404e53
      

• Job rom_ctrl-sim-vcs_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:

  • Test rom_ctrl_tl_errors has 1 failures.

    • 8.rom_ctrl_tl_errors.20234017301324724652239015560603147247881753770263783814378062897085103402886
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/8.rom_ctrl_tl_errors/latest/run.log

        Job ID: smart:987dd130-7c55-453b-81f1-1ce33afd0a79
      

• Job rom_ctrl-sim-vcs_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:

  • Test rom_ctrl_tl_errors has 1 failures.

    • 12.rom_ctrl_tl_errors.5432842583034650720715762780537321803137655358488570410849794741773936285006
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_tl_errors/latest/run.log

        Job ID: smart:3ca4d1fc-22e1-4ba7-8475-3994a0e23b17
      

• UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test rom_ctrl_stress_all has 1 failures.

    • 49.rom_ctrl_stress_all.41419330158614636477017640097684436163427107219331758892837618640576011773616
      Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/49.rom_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 40021697947 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x17a77b26
        UVM_INFO @ 40021697947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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