4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | rom_ctrl_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 115 | 0.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 0 | 50 | 0.00 | ||
| V2 | stress_all | rom_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 0 | 50 | 0.00 | ||
| V2 | alert_test | rom_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| rom_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| rom_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 240 | 0.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | tl_intg_err | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| rom_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| rom_ctrl_kmac_err_chk | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 0 | 95 | 0.00 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 500 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 0 | 0.00 |
| V2 | 6 | 6 | 0 | 0.00 |
| V2S | 4 | 4 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 502 failures:
0.rom_ctrl_smoke.99464125936260304866420323053387912352070801993016672260055017180435413943201
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_smoke/latest/run.log
1.rom_ctrl_smoke.110572458425225217528977769058801352126920491108581464205543109890704590739223
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_smoke/latest/run.log
... and 48 more failures.
0.rom_ctrl_stress_all.56938287244867009169121089887219447794684446632992671622865323327071070222148
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all/latest/run.log
1.rom_ctrl_stress_all.73741285688668805419829229846508168235938625548182217463179520881410366422327
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all/latest/run.log
... and 48 more failures.
0.rom_ctrl_max_throughput_chk.11378538953114520550827662487474014941329194976388041129742764494793032463075
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_max_throughput_chk/latest/run.log
1.rom_ctrl_max_throughput_chk.29806699811693860012232071495701911011201067297819497087971901421835525575955
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_max_throughput_chk/latest/run.log
... and 48 more failures.
0.rom_ctrl_corrupt_sig_fatal_chk.83987152464581622666583488575187457709015314907347814853062904495209257154145
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
1.rom_ctrl_corrupt_sig_fatal_chk.85037762277686154895414647290629040942745040458065391828513778080408128291525
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
... and 48 more failures.
0.rom_ctrl_kmac_err_chk.56650200696489675051466774421395496604073706840211288920885530109936627948537
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_kmac_err_chk/latest/run.log
1.rom_ctrl_kmac_err_chk.71778906343952361352623463645475610013849809151475633992387290987391909937460
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_kmac_err_chk/latest/run.log
... and 48 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.