ROM_CTRL Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: `0dd29ab736`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	37.510s	8.242ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	14.070s	1.515ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.920s	11.825ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.430s	1.580ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	12.440s	2.947ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.890s	4.072ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.920s	11.825ms	20	20	100.00
		rom_ctrl_csr_aliasing	12.440s	2.947ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	11.400s	2.485ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	7.270s	504.797us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.930s	2.121ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.847m	57.394ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.680s	17.152ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.290s	16.550ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.030s	9.956ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.030s	9.956ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	14.070s	1.515ms	5	5	100.00
		rom_ctrl_csr_rw	15.920s	11.825ms	20	20	100.00
		rom_ctrl_csr_aliasing	12.440s	2.947ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.040s	1.986ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	14.070s	1.515ms	5	5	100.00
		rom_ctrl_csr_rw	15.920s	11.825ms	20	20	100.00
		rom_ctrl_csr_aliasing	12.440s	2.947ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.040s	1.986ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	10.143m	64.561ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	6.150m	43.072ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.825m	9.007ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.314m	6.425ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.825m	9.007ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.143m	64.561ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.143m	64.561ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.143m	64.561ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.143m	64.561ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.143m	64.561ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.825m	9.007ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.825m	9.007ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	37.510s	8.242ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	37.510s	8.242ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	37.510s	8.242ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.314m	6.425ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.143m	64.561ms	49	50	98.00
		rom_ctrl_kmac_err_chk	33.680s	17.152ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	10.143m	64.561ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.143m	64.561ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	10.143m	64.561ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	6.150m	43.072ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.825m	9.007ms	5	5	100.00
V2S		TOTAL			93	95	97.89
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.928h	253.870ms	36	50	72.00
V3		TOTAL			36	50	72.00
		TOTAL			484	500	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	2	50.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.79	97.04	93.25	97.88	100.00	99.02	98.04	99.30

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 13 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.26815615727862898420772110375951710052228503445319914976342715081134061898250
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c6d1c27e-a4cb-44d4-b5bf-2288ebbb94aa
```
  - 3.rom_ctrl_stress_all_with_rand_reset.75320930861318755954234978708881216719898402622938376269317808638050465072981
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:b497b509-ae80-46ca-a218-3d6cb5027e92
```
  - ... and 11 more failures.
UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 13.rom_ctrl_passthru_mem_tl_intg_err.11252616455002034225293836705894429432608289837449436298703971258048381883962
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 10014483973 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xf2b20008
  UVM_INFO @ 10014483973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 38.rom_ctrl_stress_all_with_rand_reset.1231541474582381389761869041444409014259808864716990388053158374201925046999
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10549860497 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x7f9af2fa
  UVM_INFO @ 10549860497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 6.rom_ctrl_corrupt_sig_fatal_chk.107146260090914699037975290605327727230866619954215698375225277906140629224637
    Line 309, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 55902603730 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 55902603730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: 0dd29ab736

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0dd29ab736`