ROM_CTRL Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: 5c87d18988

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	39.220s	16.830ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	14.520s	1.481ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.910s	1.970ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	13.670s	5.562ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	9.540s	868.670us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.040s	4.170ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.910s	1.970ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.540s	868.670us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.860s	2.178ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.930s	5.255ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.650s	2.074ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.818m	65.804ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.800s	16.028ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.660s	8.468ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.790s	2.426ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.790s	2.426ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	14.520s	1.481ms	5	5	100.00
		rom_ctrl_csr_rw	15.910s	1.970ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.540s	868.670us	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.690s	10.318ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	14.520s	1.481ms	5	5	100.00
		rom_ctrl_csr_rw	15.910s	1.970ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.540s	868.670us	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.690s	10.318ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.351m	120.735ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	6.455m	84.372ms	17	20	85.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.125m	646.834us	5	5	100.00
		rom_ctrl_tl_intg_err	1.351m	2.416ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.125m	646.834us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.351m	120.735ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.351m	120.735ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.351m	120.735ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.351m	120.735ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.351m	120.735ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.125m	646.834us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.125m	646.834us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	39.220s	16.830ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	39.220s	16.830ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	39.220s	16.830ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.351m	2.416ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.351m	120.735ms	49	50	98.00
		rom_ctrl_kmac_err_chk	33.800s	16.028ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.351m	120.735ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.351m	120.735ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.351m	120.735ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	6.455m	84.372ms	17	20	85.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.125m	646.834us	5	5	100.00
V2S		TOTAL			91	95	95.79
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.694h	239.754ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			474	500	94.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	2	50.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.41	97.04	92.65	97.88	100.00	98.37	98.04	97.91

Failure Buckets

• Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 21 failures.

    • 4.rom_ctrl_stress_all_with_rand_reset.22977025770311519928218101370607782323822911926411764480396332573165286334231
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:8a1a5aa8-8a70-4727-a888-4c04261e5f5b
      

    • 6.rom_ctrl_stress_all_with_rand_reset.26524476082808152950093381584872251610315633021658886553538038955728712291383
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:66ae1abc-9573-46d0-99fb-55b0cc4b1729
      

    • ... and 19 more failures.

• UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 4 failures:

  • Test rom_ctrl_passthru_mem_tl_intg_err has 3 failures.

    • 3.rom_ctrl_passthru_mem_tl_intg_err.57899066492819894225673854197763206914673181630324162260026114991973093925624
      Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @ 10006169994 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x44788000
        UVM_INFO @ 10006169994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.rom_ctrl_passthru_mem_tl_intg_err.69619194092836650811526685955811132507162844537130959530931802861073758362054
      Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @ 10009815705 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x11ae0004
        UVM_INFO @ 10009815705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 7.rom_ctrl_stress_all_with_rand_reset.49408548992490236204694444587178398485402876886386320310319543007938399977585
      Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 11513948168 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x81b84b28
        UVM_INFO @ 11513948168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 34.rom_ctrl_corrupt_sig_fatal_chk.31111523288624363029925225634450416818755317881511842721414504519538363441070
      Line 295, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 37849782852 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 37849782852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.02.05_04.47.01
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• 2024.01.22_11.05.21
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