ROM_CTRL Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	44.540s	6.191ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.820s	1.846ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.250s	8.524ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	11.780s	4.770ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.440s	10.421ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	21.300s	8.638ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.250s	8.524ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.440s	10.421ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.650s	1.986ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	16.270s	2.098ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.800s	2.158ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.289m	61.159ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.030s	4.274ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.810s	2.049ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.880s	3.356ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.880s	3.356ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.820s	1.846ms	5	5	100.00
		rom_ctrl_csr_rw	16.250s	8.524ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.440s	10.421ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.020s	2.174ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.820s	1.846ms	5	5	100.00
		rom_ctrl_csr_rw	16.250s	8.524ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.440s	10.421ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.020s	2.174ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.189m	173.797ms	28	50	56.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.509m	10.812ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.825m	16.656ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.325m	2.013ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.825m	16.656ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.189m	173.797ms	28	50	56.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.189m	173.797ms	28	50	56.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.189m	173.797ms	28	50	56.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.189m	173.797ms	28	50	56.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.189m	173.797ms	28	50	56.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.825m	16.656ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.825m	16.656ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	44.540s	6.191ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	44.540s	6.191ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	44.540s	6.191ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.325m	2.013ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.189m	173.797ms	28	50	56.00
		rom_ctrl_kmac_err_chk	35.030s	4.274ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.189m	173.797ms	28	50	56.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.189m	173.797ms	28	50	56.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.189m	173.797ms	28	50	56.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.509m	10.812ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.825m	16.656ms	5	5	100.00
V2S		TOTAL			73	95	76.84
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.851h	301.801ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			438	500	87.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.43	97.04	92.50	97.88	100.00	98.37	98.04	98.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:756) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 31 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 31 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.99080930698955346498028894201895458145709819566107635045760803480757789721583
    Line 315, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6242709859 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 6242709859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.37088408052466890483329519790614957326466594772206573321707636665620959669281
    Line 324, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29289043384 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 29289043384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 20 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 20 failures.
  - 3.rom_ctrl_corrupt_sig_fatal_chk.38960900738302386560981218593573284566341608622049711910730536780080417022939
    Line 303, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_corrupt_sig_fatal_chk_vseq.sv, 300
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 4.rom_ctrl_corrupt_sig_fatal_chk.44411312963493337718676400894962230611365366886860107823918665064881967980662
    Line 328, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_corrupt_sig_fatal_chk_vseq.sv, 300
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 18 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.87100659111166557361427510352250638204188347840119778718074332324371903786566
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:75a83ded-4184-4bc3-a035-dd95c03adef2
```
  - 9.rom_ctrl_stress_all_with_rand_reset.75498608290698506671163888978213600229695932208316956807350501223482132497981
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:fb85aa14-ec44-442a-a86a-335e3c5e4ea4
```
  - ... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 12.rom_ctrl_stress_all_with_rand_reset.111367607632660248446874763272488487993989096896400464473581996872213157725412
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10007766162 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xa5a658cc
  UVM_INFO @ 10007766162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.rom_ctrl_stress_all_with_rand_reset.48321246189451783952624527930863563783405487550148962511484109227458192780858
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10870127675 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x355dfd82
  UVM_INFO @ 10870127675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:595) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 2 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.
  - 6.rom_ctrl_corrupt_sig_fatal_chk.23494046542972289340854771903867042740376965218396841337225214217365823401492
    Line 263, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 2620323201 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
  UVM_INFO @ 2620323201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.rom_ctrl_corrupt_sig_fatal_chk.63311445569440983877428671709784681332851743701279104614902930046502843864281
    Line 282, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 3558454986 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
  UVM_INFO @ 3558454986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: 8faf04697a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8faf04697a`