ROM_CTRL Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	38.350s	3.883ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.780s	6.677ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.050s	7.936ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.080s	3.697ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.800s	7.837ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.920s	6.262ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.050s	7.936ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.800s	7.837ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.370s	1.616ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.940s	3.536ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.260s	10.168ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.685m	49.498ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.000s	14.478ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.540s	2.036ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.460s	6.863ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.460s	6.863ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.780s	6.677ms	5	5	100.00
		rom_ctrl_csr_rw	16.050s	7.936ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.800s	7.837ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.120s	5.586ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.780s	6.677ms	5	5	100.00
		rom_ctrl_csr_rw	16.050s	7.936ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.800s	7.837ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.120s	5.586ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.166m	56.842ms	31	50	62.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.603m	50.632ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.805m	2.838ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.373m	2.415ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.805m	2.838ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.166m	56.842ms	31	50	62.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.166m	56.842ms	31	50	62.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.166m	56.842ms	31	50	62.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.166m	56.842ms	31	50	62.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.166m	56.842ms	31	50	62.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.805m	2.838ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.805m	2.838ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	38.350s	3.883ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	38.350s	3.883ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	38.350s	3.883ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.373m	2.415ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.166m	56.842ms	31	50	62.00
		rom_ctrl_kmac_err_chk	35.000s	14.478ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.166m	56.842ms	31	50	62.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.166m	56.842ms	31	50	62.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.166m	56.842ms	31	50	62.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.603m	50.632ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.805m	2.838ms	5	5	100.00
V2S		TOTAL			76	95	80.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.947h	128.293ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			448	500	89.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.45	97.04	92.65	97.88	100.00	98.37	98.04	98.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:774) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 25 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 25 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.25921826545331563771747232760004950329471088083052890986023153556110741994948
    Line 281, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7416016620 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 7416016620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.1320198092545935430244370149535062399849424038489722280974287401274287960144
    Line 399, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 106041096475 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 106041096475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 18 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 18 failures.
  - 2.rom_ctrl_corrupt_sig_fatal_chk.41257797483603797969576073652850669969332827433526474572368005243949045129371
    Line 292, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_corrupt_sig_fatal_chk_vseq.sv, 264
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 3.rom_ctrl_corrupt_sig_fatal_chk.28534182286289740503737487156583904640580480462775791831555899326927831048343
    Line 304, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_corrupt_sig_fatal_chk_vseq.sv, 264
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 16 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.4439983135446322439737867833207376480922038096522731249520219534143266658423
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:31721aea-8f5d-476c-b9d0-13d1da220de3
```
  - 10.rom_ctrl_stress_all_with_rand_reset.65906332127551996691094826030965592177900577086614543337636785450351065760382
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:5fd4cc95-b877-41c2-ba41-d3bd1fcb4249
```
  - ... and 5 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 9.rom_ctrl_stress_all_with_rand_reset.82064843131481676641385242104346719246585455058943157343400006227257566396901
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11357789020 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x100bc8b1
  UVM_INFO @ 11357789020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:600) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 34.rom_ctrl_corrupt_sig_fatal_chk.27400549729962718360897965010387498068677094664586257738904096181056700848304
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 113801051 ps: (cip_base_vseq.sv:600) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
  UVM_INFO @ 113801051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: df66f8a42e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `df66f8a42e`