ROM_CTRL Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: `49a27e136c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	45.790s	17.411ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.220s	8.263ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	17.700s	23.740ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.220s	6.759ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	13.800s	6.180ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.370s	8.009ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	17.700s	23.740ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.800s	6.180ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	12.030s	18.194ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.540s	2.120ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.780s	2.228ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.790m	183.252ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.140s	4.297ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.770s	2.258ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.390s	3.669ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.390s	3.669ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.220s	8.263ms	5	5	100.00
		rom_ctrl_csr_rw	17.700s	23.740ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.800s	6.180ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.280s	2.086ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.220s	8.263ms	5	5	100.00
		rom_ctrl_csr_rw	17.700s	23.740ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.800s	6.180ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.280s	2.086ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	10.016m	62.981ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.445m	39.394ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.106m	5.117ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.327m	2.282ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.106m	5.117ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.016m	62.981ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.016m	62.981ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.016m	62.981ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.016m	62.981ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.016m	62.981ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.106m	5.117ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.106m	5.117ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	45.790s	17.411ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	45.790s	17.411ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	45.790s	17.411ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.327m	2.282ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.016m	62.981ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.140s	4.297ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	10.016m	62.981ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.016m	62.981ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	10.016m	62.981ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.445m	39.394ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.106m	5.117ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.849h	21.756ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			464	500	92.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.61	97.04	92.80	97.88	100.00	98.69	98.04	98.84

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:774) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 24 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 24 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.90087473207751725373178756040981580391129761274071059299884606295889416754532
    Line 479, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 95486410599 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 95486410599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.114440220762444371373674609087219166455839983875350577421293637625605041018694
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1744314013 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 1744314013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 8.rom_ctrl_stress_all_with_rand_reset.114820868078320670407814118843935637765409197011739002008958344117885585252389
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:9a5f84a0-211d-4ec9-b7c9-68ff4116b5ad
```
  - 11.rom_ctrl_stress_all_with_rand_reset.39699124225998181136228882951285145718221137787659329982993961802348768624575
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:cc1a3181-c97e-4a1e-ba2a-0a478e8a3fed
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.72702123952034517047861787387292094989626524121623647145800298100610302336485
    Line 270, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 15687155398 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x60f3f7d5
  UVM_INFO @ 15687155398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.rom_ctrl_stress_all_with_rand_reset.19347636987833527684251238117959482017878916249510918200344652409470964883377
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10724859313 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xca006db7
  UVM_INFO @ 10724859313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 14.rom_ctrl_stress_all_with_rand_reset.12718660565640198457392816474785382861102900885966013776493253194672617993903
    Line 455, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 291780584784 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 291780584784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: 49a27e136c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `49a27e136c`