ROM_CTRL Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	42.770s	4.168ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.140s	1.572ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.900s	2.189ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.760s	3.662ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.220s	23.003ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.420s	2.141ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.900s	2.189ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.220s	23.003ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	12.670s	24.499ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.620s	1.668ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.150s	4.050ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.858m	10.965ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.200s	7.636ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.820s	2.243ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	21.440s	2.242ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	21.440s	2.242ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.140s	1.572ms	5	5	100.00
		rom_ctrl_csr_rw	16.900s	2.189ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.220s	23.003ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.520s	2.085ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.140s	1.572ms	5	5	100.00
		rom_ctrl_csr_rw	16.900s	2.189ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.220s	23.003ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.520s	2.085ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.150m	89.502ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.598m	12.865ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.786m	2.640ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.313m	4.193ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.786m	2.640ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.150m	89.502ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.150m	89.502ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.150m	89.502ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.150m	89.502ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.150m	89.502ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.786m	2.640ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.786m	2.640ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	42.770s	4.168ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	42.770s	4.168ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	42.770s	4.168ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.313m	4.193ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.150m	89.502ms	49	50	98.00
		rom_ctrl_kmac_err_chk	33.200s	7.636ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.150m	89.502ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.150m	89.502ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.150m	89.502ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.598m	12.865ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.786m	2.640ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.259h	22.920ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			471	500	94.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.45	97.04	92.65	97.88	100.00	98.37	98.04	98.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:788) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 22 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.98959368264386293908039341534984305116659359729125162088231756243757829284127
    Line 372, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 67355697552 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 67355697552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rom_ctrl_stress_all_with_rand_reset.3137043750828285248684411383876787524387704537130502930855491230884661241371
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 447953411 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 447953411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 8.rom_ctrl_stress_all_with_rand_reset.126949814625554145457236278477659390831022718449092411172687693937462025209
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:7eaac097-2cd8-4e39-8517-d63e0ff78762
```
  - 25.rom_ctrl_stress_all_with_rand_reset.80648466448209676117104849282869059219982007593642753954469179126790551247185
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:68db7f2d-aa34-4d87-92de-1104f60f9763
```
  - ... and 4 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 2.rom_ctrl_corrupt_sig_fatal_chk.82891717775593477235015265479924438329002817953626184610594229666989089462152
    Line 294, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 28908722452 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 28908722452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: e0c4026501

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e0c4026501`