ROM_CTRL Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: `0cdf265eaa`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	41.630s	4.205ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.460s	2.179ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.800s	5.797ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	13.660s	1.566ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.510s	19.828ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.280s	33.642ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.800s	5.797ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.510s	19.828ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.340s	13.055ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.270s	1.942ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.400s	4.225ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.788m	24.137ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	36.570s	4.256ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.890s	8.352ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.550s	1.926ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.550s	1.926ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.460s	2.179ms	5	5	100.00
		rom_ctrl_csr_rw	15.800s	5.797ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.510s	19.828ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.910s	15.372ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.460s	2.179ms	5	5	100.00
		rom_ctrl_csr_rw	15.800s	5.797ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.510s	19.828ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.910s	15.372ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.901m	58.841ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.483m	10.393ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.822m	2.629ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.345m	22.798ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.822m	2.629ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.901m	58.841ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.901m	58.841ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.901m	58.841ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.901m	58.841ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.901m	58.841ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.822m	2.629ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.822m	2.629ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	41.630s	4.205ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	41.630s	4.205ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	41.630s	4.205ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.345m	22.798ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.901m	58.841ms	50	50	100.00
		rom_ctrl_kmac_err_chk	36.570s	4.256ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.901m	58.841ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.901m	58.841ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.901m	58.841ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.483m	10.393ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.822m	2.629ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.943h	70.684ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			467	500	93.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.45	97.04	92.65	97.88	100.00	98.37	98.04	98.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:815) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 23 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.11255894431987528496390912936151762859204360322077657334314067624084939442867
    Line 485, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28880389005 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 28880389005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rom_ctrl_stress_all_with_rand_reset.85314095212980284848226607135579849756427269835694678304255943379480178468716
    Line 408, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26275020437 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26275020437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 9 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.8101402130319843090689201919973361129568388173275147005120435583827673549080
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:9667cd11-1392-4f6f-9b2a-13770523b67b
```
  - 3.rom_ctrl_stress_all_with_rand_reset.93443720280212963285342873500274040475856111073150675022165284269691171405324
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:cafc7d70-1fec-4024-adfe-36b90d6bfb6c
```
  - ... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 36.rom_ctrl_stress_all_with_rand_reset.88869789439333973951331857673824428427266263311555834133330543572978264925124
    Line 282, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 25810478004 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x2fbf07fe
  UVM_INFO @ 25810478004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: 0cdf265eaa

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0cdf265eaa`