ROM_CTRL/32KB Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.498m	10.412ms	48	50	96.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	31.930s	13.527ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	34.240s	16.379ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	32.770s	20.276ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	28.600s	3.859ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	34.190s	4.174ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	34.240s	16.379ms	20	20	100.00
		rom_ctrl_csr_aliasing	28.600s	3.859ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	24.270s	30.010ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	28.150s	5.964ms	5	5	100.00
V1		TOTAL			113	115	98.26
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	36.510s	17.102ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.465m	23.524ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.174m	17.408ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	34.630s	20.216ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	39.470s	38.677ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	39.470s	38.677ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	31.930s	13.527ms	5	5	100.00
		rom_ctrl_csr_rw	34.240s	16.379ms	20	20	100.00
		rom_ctrl_csr_aliasing	28.600s	3.859ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	31.750s	13.424ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	31.930s	13.527ms	5	5	100.00
		rom_ctrl_csr_rw	34.240s	16.379ms	20	20	100.00
		rom_ctrl_csr_aliasing	28.600s	3.859ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	31.750s	13.424ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	14.226m	173.549ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.352m	23.112ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.089m	17.715ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.807m	3.138ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.089m	17.715ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.226m	173.549ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.226m	173.549ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	14.226m	173.549ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.226m	173.549ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.226m	173.549ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.089m	17.715ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.089m	17.715ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.498m	10.412ms	48	50	96.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.498m	10.412ms	48	50	96.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.498m	10.412ms	48	50	96.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.807m	3.138ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	14.226m	173.549ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.174m	17.408ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	14.226m	173.549ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.226m	173.549ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	14.226m	173.549ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.352m	23.112ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.089m	17.715ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.829h	55.415ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			458	500	91.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.51	96.96	92.97	97.88	100.00	98.36	98.04	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 28 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.109438579552581199432639408561223926990142346290220665777767395024163072474582
    Line 437, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 50547855859 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 50547855859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.56719495318573884553554941108335499436420206235150100894648312665211947980673
    Line 307, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19839694605 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19839694605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.6777104603423626097169211834973684508973861393007054893723722075344913035867
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e7de4e3b-8191-4d11-8fbf-570aa927b590
```
  - 1.rom_ctrl_stress_all_with_rand_reset.35681348866420016614806435432358794343420874506863577438430389471634917910269
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:6b948b8c-394e-4e6b-a1ec-b5853de108c7
```
  - ... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.97720967705015066038848636983445810122822777126511243144141461192469357579618
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11521656611 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xb21b0165
  UVM_INFO @ 11521656611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.rom_ctrl_stress_all_with_rand_reset.13951155245375284461563206609376885929303561833280294362095906551108608992387
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10479150937 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xda35fba9
  UVM_INFO @ 10479150937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 3 failures:

Test rom_ctrl_stress_all has 1 failures.

7.rom_ctrl_stress_all.18727237600456797727752669729272556943031450703510427352702477300866519620234
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/7.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 40018303003 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x408f2572
  UVM_INFO @ 40018303003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_ctrl_smoke has 2 failures.

12.rom_ctrl_smoke.107259773554093025762916414135811634158724023240701159568518541069838540818261
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 40018128366 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x6a2996c5
  UVM_INFO @ 40018128366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.rom_ctrl_smoke.40312657200422536940888291077807606001972033510944484794595160297898009649261
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/34.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 40014717783 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x7d06e8b1
  UVM_INFO @ 40014717783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---