ROM_CTRL/32KB Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	40.340s	15.703ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.820s	7.898ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.950s	8.777ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.050s	2.018ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.080s	6.982ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.750s	12.077ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.950s	8.777ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.080s	6.982ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.030s	7.266ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.790s	1.431ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.440s	2.165ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.304m	60.629ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.610s	4.249ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.600s	7.606ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.590s	1.911ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.590s	1.911ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.820s	7.898ms	5	5	100.00
		rom_ctrl_csr_rw	14.950s	8.777ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.080s	6.982ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.220s	4.374ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.820s	7.898ms	5	5	100.00
		rom_ctrl_csr_rw	14.950s	8.777ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.080s	6.982ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.220s	4.374ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.669m	52.838ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.280m	33.596ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.878m	1.535ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.299m	7.718ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.878m	1.535ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.669m	52.838ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.669m	52.838ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.669m	52.838ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.669m	52.838ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.669m	52.838ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.878m	1.535ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.878m	1.535ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	40.340s	15.703ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	40.340s	15.703ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	40.340s	15.703ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.299m	7.718ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.669m	52.838ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.610s	4.249ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.669m	52.838ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.669m	52.838ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.669m	52.838ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.280m	33.596ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.878m	1.535ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.517h	16.592ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			468	500	93.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	96.97	93.01	97.88	100.00	98.37	98.03	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 18 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.31818957995700868115346834099434458356331454982721995171236954241716121256301
    Line 286, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16432667836 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16432667836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.14461681290196927577253931948952042605530721194817418522712719078430145077556
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 596339914 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 596339914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.50607465826439454659095374570556979980115167303845271863749491635563281172203
    Line 259, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12069269912 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x108c4d6f
  UVM_INFO @ 12069269912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.rom_ctrl_stress_all_with_rand_reset.63355803563839821918544998340656982903726795290191623772336113075957374080697
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11943160914 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xd04b5569
  UVM_INFO @ 11943160914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.34838293038810105356635340687640249705115181471783911976200854641992308658629
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a95926be-9a5a-431e-bd26-c80af6b1c80f
```
  - 5.rom_ctrl_stress_all_with_rand_reset.109858988220883841718264607474411774992896293731317845267860995398737536390067
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e712cfad-e509-49d7-8884-828f767e3c73
```
  - ... and 5 more failures.

ROM_CTRL/32KB Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d0c52cdadd`