ROM_CTRL/32KB Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	34.240s	8.558ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	12.740s	4.921ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.450s	2.134ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	12.790s	1.315ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.940s	4.503ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.660s	4.385ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.450s	2.134ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.940s	4.503ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.910s	3.700ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.660s	8.059ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.580s	4.049ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.684m	13.272ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.720s	4.201ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.210s	23.646ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.750s	8.860ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.750s	8.860ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	12.740s	4.921ms	5	5	100.00
		rom_ctrl_csr_rw	16.450s	2.134ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.940s	4.503ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.810s	2.107ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	12.740s	4.921ms	5	5	100.00
		rom_ctrl_csr_rw	16.450s	2.134ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.940s	4.503ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.810s	2.107ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	6.432m	543.089ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.655m	50.266ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.765m	1.477ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.323m	1.848ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.765m	1.477ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.432m	543.089ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.432m	543.089ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.432m	543.089ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.432m	543.089ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.432m	543.089ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.765m	1.477ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.765m	1.477ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	34.240s	8.558ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	34.240s	8.558ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	34.240s	8.558ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.323m	1.848ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.432m	543.089ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.720s	4.201ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	6.432m	543.089ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.432m	543.089ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	6.432m	543.089ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.655m	50.266ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.765m	1.477ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.925h	38.872ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			468	500	93.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	96.97	93.01	97.88	100.00	98.37	98.03	99.07

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 23 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.26175624033844046617785770074726674214998598293017377711212313534186503434092
      Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 593310904 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 593310904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rom_ctrl_stress_all_with_rand_reset.47224565010476638547097229537051705862452479868887527350924482813058928309391
      Line 417, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23306448994 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 23306448994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 9 failures.

    • 2.rom_ctrl_stress_all_with_rand_reset.65268047487147933601572266628885258128448752625401767653738929122509625514355
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:1764e603-15f8-4146-901c-875edcbcca3e
      

    • 4.rom_ctrl_stress_all_with_rand_reset.46440278595817271097607678393808710101754848788199422717576232607341885283469
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:5c299e1c-8524-4b14-8b92-fe7614bbcbe2
      

    • ... and 7 more failures.

Past Results

• Latest
• 2024.05.15_03.01.54
• 2024.05.13_03.50.39
• 2024.05.10_04.37.49
• 2024.05.08_03.47.19
• 2024.05.06_05.03.06
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