ROM_CTRL/32KB Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	40.260s	6.751ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.190s	7.891ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.190s	15.375ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.100s	2.075ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.140s	7.247ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.780s	2.126ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.190s	15.375ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.140s	7.247ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.860s	2.121ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.680s	1.706ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.390s	2.211ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.516m	18.340ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.030s	17.505ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.240s	26.057ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.320s	8.212ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.320s	8.212ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.190s	7.891ms	5	5	100.00
		rom_ctrl_csr_rw	16.190s	15.375ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.140s	7.247ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.080s	8.185ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.190s	7.891ms	5	5	100.00
		rom_ctrl_csr_rw	16.190s	15.375ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.140s	7.247ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.080s	8.185ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.575m	47.934ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.349m	9.119ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.633m	1.976ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.276m	7.121ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.633m	1.976ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.575m	47.934ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.575m	47.934ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.575m	47.934ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.575m	47.934ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.575m	47.934ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.633m	1.976ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.633m	1.976ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	40.260s	6.751ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	40.260s	6.751ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	40.260s	6.751ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.276m	7.121ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.575m	47.934ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.030s	17.505ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.575m	47.934ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.575m	47.934ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.575m	47.934ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.349m	9.119ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.633m	1.976ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.529h	63.424ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			471	500	94.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.52	96.97	93.01	97.88	100.00	98.37	98.03	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 22 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.57415268640370404406155564963840540009524378531737889883529294289947532596563
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 521852482 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 521852482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rom_ctrl_stress_all_with_rand_reset.111814826479744245143832186826572901338212128266146005915189214316450582468059
    Line 336, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10817866485 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10817866485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.27716009808718450703051347238129272025779246095488783577839710169215344409673
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ad9c39b6-6f3e-4337-a7d8-d2648465e9c9
```
  - 7.rom_ctrl_stress_all_with_rand_reset.41210741519230064730633927845039588100671724742530877844369064648361223679990
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:224fc9f5-db44-471b-bb04-ee7cfb7aa572
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 16.rom_ctrl_stress_all_with_rand_reset.96648635651145556035433018482506088739366006788588570873220548315748439964574
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12088518626 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xe8d1aaba
  UVM_INFO @ 12088518626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.rom_ctrl_stress_all_with_rand_reset.4002587137236922330354265179874777138754488735595224312507389791391885975264
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12728905463 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x9bd33a46
  UVM_INFO @ 12728905463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `9656691e03`