ROM_CTRL/32KB Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: `18c8953cf1`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	43.460s	32.853ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	19.050s	2.103ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.290s	8.241ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.170s	1.820ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.210s	8.506ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.210s	2.072ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.290s	8.241ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.210s	8.506ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	12.130s	5.861ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	16.030s	7.718ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.060s	8.542ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.744m	11.595ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	32.630s	4.269ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	16.820s	8.390ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.890s	1.888ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.890s	1.888ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	19.050s	2.103ms	5	5	100.00
		rom_ctrl_csr_rw	16.290s	8.241ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.210s	8.506ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.590s	1.921ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	19.050s	2.103ms	5	5	100.00
		rom_ctrl_csr_rw	16.290s	8.241ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.210s	8.506ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.590s	1.921ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.739m	98.488ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.724m	12.551ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.074m	3.751ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.356m	1.989ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.074m	3.751ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.739m	98.488ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.739m	98.488ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.739m	98.488ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.739m	98.488ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.739m	98.488ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.074m	3.751ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.074m	3.751ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	43.460s	32.853ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	43.460s	32.853ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	43.460s	32.853ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.356m	1.989ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.739m	98.488ms	50	50	100.00
		rom_ctrl_kmac_err_chk	32.630s	4.269ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.739m	98.488ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.739m	98.488ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.739m	98.488ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.724m	12.551ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.074m	3.751ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.952h	186.272ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			462	500	92.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.57	96.97	93.01	97.88	100.00	98.69	98.03	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 26 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.84917826740910848475971357165178405119443660785119138633073808952402720959838
    Line 334, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 48774634038 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 48774634038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.83742034400674433601327811876313720634911223751187720426215597988735754948572
    Line 347, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29063972153 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 29063972153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 6.rom_ctrl_stress_all_with_rand_reset.91965807655588329580059419415555433121904103657022882169748910010565909268641
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e0791476-0343-45d9-8e6d-d1797de99b79
```
  - 31.rom_ctrl_stress_all_with_rand_reset.72013662625953675432835867835803004656297043590069139923675203345640341748049
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:6c1edc90-5bab-4f74-9e23-1ad8951f44fe
```
  - ... and 5 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.93705812967396675799459752983165467743583507383163988821560558299516974679171
    Line 878, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1240528364024 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 1240528364024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.rom_ctrl_stress_all_with_rand_reset.69445399628217215458842480321212300155653001359156902816591351483575488124105
    Line 797, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 735039467689 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 735039467689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 37.rom_ctrl_kmac_err_chk.103928011272176764639855892866075298701774717197864237806535100168822619625070
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 2761729911 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 2761729911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.113775777058761860616775353579797179817085703382320999646715472570698602352859
    Line 261, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10090380044 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xccde93ac
  UVM_INFO @ 10090380044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.rom_ctrl_stress_all_with_rand_reset.48928164322297997657342504497337341028836295139020379411486068907268060747987
    Line 330, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 145136851010 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xf04aac13
  UVM_INFO @ 145136851010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: 18c8953cf1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `18c8953cf1`