69c572b503| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 46.310s | 17.126ms | 48 | 50 | 96.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 20.050s | 8.940ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 15.040s | 3.935ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 15.460s | 2.054ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 16.810s | 4.101ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 16.300s | 4.203ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 15.040s | 3.935ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 16.810s | 4.101ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 12.530s | 2.827ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 15.410s | 5.442ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 113 | 115 | 98.26 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 17.620s | 2.232ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 1.868m | 21.107ms | 49 | 50 | 98.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 35.250s | 8.793ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 17.790s | 4.278ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 20.150s | 7.343ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 20.150s | 7.343ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 20.050s | 8.940ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 15.040s | 3.935ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 16.810s | 4.101ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 18.350s | 30.735ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 20.050s | 8.940ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 15.040s | 3.935ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 16.810s | 4.101ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 18.350s | 30.735ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 239 | 240 | 99.58 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 8.569m | 53.487ms | 50 | 50 | 100.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 1.703m | 46.545ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 1.804m | 1.675ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 1.300m | 36.509ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.804m | 1.675ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.569m | 53.487ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.569m | 53.487ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 8.569m | 53.487ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.569m | 53.487ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.569m | 53.487ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.804m | 1.675ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.804m | 1.675ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 46.310s | 17.126ms | 48 | 50 | 96.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 46.310s | 17.126ms | 48 | 50 | 96.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 46.310s | 17.126ms | 48 | 50 | 96.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.300m | 36.509ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 8.569m | 53.487ms | 50 | 50 | 100.00 |
| rom_ctrl_kmac_err_chk | 35.250s | 8.793ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 8.569m | 53.487ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.569m | 53.487ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 8.569m | 53.487ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 1.703m | 46.545ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.804m | 1.675ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 95 | 95 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.911h | 188.649ms | 12 | 50 | 24.00 |
| V3 | TOTAL | 12 | 50 | 24.00 | |||
| TOTAL | 459 | 500 | 91.80 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 6 | 6 | 5 | 83.33 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.49 | 96.97 | 93.01 | 97.88 | 100.00 | 98.37 | 98.03 | 98.14 |
UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
0.rom_ctrl_stress_all_with_rand_reset.113884265543912784926256389687050600108409637603872846715417682327974601608398
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1836792871 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1836792871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rom_ctrl_stress_all_with_rand_reset.38727717098195072839611665560411445840778275582651089932988312791325057302959
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 109262595 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 109262595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
1.rom_ctrl_stress_all_with_rand_reset.45777551514433897057401827805400704616114913980015586021427632347104606429034
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:810ffa8d-4a46-4585-8eea-a388b0696fd9
2.rom_ctrl_stress_all_with_rand_reset.14165897722763464143158884961399848359815606090517735707164476998855742943422
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:0d185d77-96c4-48a6-b4e8-e3343dc46bb8
... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
4.rom_ctrl_smoke.43480913990847291551741574733897124489237113740863374484344825258680342879018
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 79951109851 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x1c7bb0bb
UVM_INFO @ 79951109851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.rom_ctrl_smoke.63367372418883207254132110597683496265568399669253261759680070095585832777134
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 40012730277 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xa9900c2e
UVM_INFO @ 40012730277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
5.rom_ctrl_stress_all.34396743903692784590214577268445938114961359831005002359707907180904356533321
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all/latest/run.log
UVM_ERROR @ 1667534919 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 1667534919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---