ROM_CTRL/32KB Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: `eb776817a5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	38.730s	14.689ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.940s	4.253ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.960s	2.133ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.900s	7.237ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.440s	4.093ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.280s	2.000ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.960s	2.133ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.440s	4.093ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.590s	3.570ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.560s	4.119ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.600s	9.316ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.767m	41.049ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.900s	8.477ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.110s	8.238ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.970s	10.778ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.970s	10.778ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.940s	4.253ms	5	5	100.00
		rom_ctrl_csr_rw	16.960s	2.133ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.440s	4.093ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.450s	8.762ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.940s	4.253ms	5	5	100.00
		rom_ctrl_csr_rw	16.960s	2.133ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.440s	4.093ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.450s	8.762ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	10.199m	80.669ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.587m	47.524ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.120m	9.197ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.283m	1.726ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.120m	9.197ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.199m	80.669ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.199m	80.669ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.199m	80.669ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.199m	80.669ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.199m	80.669ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.120m	9.197ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.120m	9.197ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	38.730s	14.689ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	38.730s	14.689ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	38.730s	14.689ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.283m	1.726ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.199m	80.669ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.900s	8.477ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	10.199m	80.669ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.199m	80.669ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	10.199m	80.669ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.587m	47.524ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.120m	9.197ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.535h	177.930ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			464	500	92.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.69	96.97	93.58	97.88	100.00	99.02	98.03	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 25 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.76160852710817787808388292749371960049202837249198181408726535931638051124707
    Line 388, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 90968252067 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 90968252067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.12575019562655571685939537155744077383976869381260028127556088478659067871638
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 726199049 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 726199049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 9 failures.
  - 10.rom_ctrl_stress_all_with_rand_reset.1881357117004501169670430235828530482195103121070753442961308483939393455116
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1a5734bb-f3f9-4280-bd3a-9f06a4c43042
```
  - 23.rom_ctrl_stress_all_with_rand_reset.71904554448591299106384016589616957614895104581539324970081114869976284552933
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:7ea78c57-fd36-4018-a072-037ce45762e1
```
  - ... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.62070660355229096912882306937705142857323227590322915071471190478000882974168
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10017946869 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x9a7172eb
  UVM_INFO @ 10017946869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.rom_ctrl_stress_all_with_rand_reset.44088125648798189364714257396524724223909092156770337817108564945158444140819
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10013150934 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x381a7fe7
  UVM_INFO @ 10013150934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: eb776817a5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `eb776817a5`