ROM_CTRL/32KB Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: `be3d980075`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	43.260s	16.166ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	20.050s	9.614ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.920s	10.995ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.190s	6.727ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.770s	12.741ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.830s	16.748ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.920s	10.995ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.770s	12.741ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.760s	7.356ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.650s	3.694ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.450s	14.485ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.883m	36.697ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.460s	21.168ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	17.320s	8.822ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.840s	2.125ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.840s	2.125ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	20.050s	9.614ms	5	5	100.00
		rom_ctrl_csr_rw	16.920s	10.995ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.770s	12.741ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.860s	10.300ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	20.050s	9.614ms	5	5	100.00
		rom_ctrl_csr_rw	16.920s	10.995ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.770s	12.741ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.860s	10.300ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.111m	540.917ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.580m	74.158ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.872m	2.467ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.361m	2.383ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.872m	2.467ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.111m	540.917ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.111m	540.917ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.111m	540.917ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.111m	540.917ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.111m	540.917ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.872m	2.467ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.872m	2.467ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	43.260s	16.166ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	43.260s	16.166ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	43.260s	16.166ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.361m	2.383ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.111m	540.917ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.460s	21.168ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.111m	540.917ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.111m	540.917ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.111m	540.917ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.580m	74.158ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.872m	2.467ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.273h	64.413ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			464	500	92.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	96.97	93.44	97.88	100.00	98.69	98.03	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 19 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.104304828533248166946235083991080532575035842275122257225411185077614000434406
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2778203810 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2778203810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.37031145931880835954665241429767096754607470076292010122970795828271006034631
    Line 346, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9670629127 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9670629127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 15 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.60445829458416515212483876970697158925676141364410572622538577994017721921470
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:038191cc-b776-4e30-9182-ade60903f8f5
```
  - 4.rom_ctrl_stress_all_with_rand_reset.23192420517277941133451938546482575680276812539120957916449454075155454924081
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:5336ac08-cdf2-4c50-8760-a8ca73a002a6
```
  - ... and 13 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 26.rom_ctrl_kmac_err_chk.39650990930993598179949696856965903418427406957807497919181073832222179378559
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 2756302633 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 2756302633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 42.rom_ctrl_stress_all_with_rand_reset.43676073199794241261014400248164436790771244496479377222404038067170898599956
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10859068387 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3861bdb2
  UVM_INFO @ 10859068387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `be3d980075`