ROM_CTRL/32KB Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: `1579f6a912`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	38.810s	3.129ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.280s	3.376ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.770s	4.361ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.960s	8.142ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	13.890s	6.652ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.280s	13.774ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.770s	4.361ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.890s	6.652ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	16.410s	2.448ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.510s	2.169ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.610s	8.504ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.390m	32.311ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.250s	17.816ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.190s	2.187ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.420s	2.208ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.420s	2.208ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.280s	3.376ms	5	5	100.00
		rom_ctrl_csr_rw	16.770s	4.361ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.890s	6.652ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.010s	20.237ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.280s	3.376ms	5	5	100.00
		rom_ctrl_csr_rw	16.770s	4.361ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.890s	6.652ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.010s	20.237ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.777m	59.731ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.327m	9.451ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.815m	5.475ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.288m	11.361ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.815m	5.475ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.777m	59.731ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.777m	59.731ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.777m	59.731ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.777m	59.731ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.777m	59.731ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.815m	5.475ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.815m	5.475ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	38.810s	3.129ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	38.810s	3.129ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	38.810s	3.129ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.288m	11.361ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.777m	59.731ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.250s	17.816ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.777m	59.731ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.777m	59.731ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.777m	59.731ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.327m	9.451ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.815m	5.475ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.739h	37.925ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			462	500	92.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.58	96.97	92.87	97.88	100.00	98.37	97.88	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 28 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.63717883891766555023502162789047807916204596805406050446047970748640160372432
    Line 435, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 70798917256 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 70798917256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.rom_ctrl_stress_all_with_rand_reset.58900282227638492809971150764251123832992207577157914126254731393378366373966
    Line 365, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 86607676890 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 86607676890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 9 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.103975923750106684444092598423622200651006001959543345639900662405852778035917
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:974a7702-7481-44cd-9f66-a75311b32bb3
```
  - 8.rom_ctrl_stress_all_with_rand_reset.100842908589476367078962786727045819410331411757372487103338392803810293840086
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8c62e47b-4479-4782-b0eb-849c57cac204
```
  - ... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.35954171059307745344277067253462030701616641906962836027250420490455421172233
    Line 259, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11921852273 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x833ef0af
  UVM_INFO @ 11921852273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: 1579f6a912

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `1579f6a912`