ROM_CTRL/32KB Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	42.030s	17.890ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.770s	7.134ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.210s	4.101ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.110s	3.423ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.290s	6.485ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.300s	4.349ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.210s	4.101ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.290s	6.485ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.780s	6.901ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.170s	7.837ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.840s	2.200ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.299m	24.743ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	32.530s	3.858ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.730s	8.648ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.080s	2.144ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.080s	2.144ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.770s	7.134ms	5	5	100.00
		rom_ctrl_csr_rw	16.210s	4.101ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.290s	6.485ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.340s	3.667ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.770s	7.134ms	5	5	100.00
		rom_ctrl_csr_rw	16.210s	4.101ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.290s	6.485ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.340s	3.667ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.375m	229.878ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.655m	48.041ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.848m	9.382ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.314m	9.762ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.848m	9.382ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.375m	229.878ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.375m	229.878ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.375m	229.878ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.375m	229.878ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.375m	229.878ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.848m	9.382ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.848m	9.382ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	42.030s	17.890ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	42.030s	17.890ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	42.030s	17.890ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.314m	9.762ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.375m	229.878ms	50	50	100.00
		rom_ctrl_kmac_err_chk	32.530s	3.858ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.375m	229.878ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.375m	229.878ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.375m	229.878ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.655m	48.041ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.848m	9.382ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.911h	37.427ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			471	500	94.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.60	96.97	93.02	97.88	100.00	98.37	97.89	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 23 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.87247269330883967260580725931840747156595415084635675367070974903978056158505
    Line 583, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28719348731 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 28719348731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.81474351546001756025334523641445387597484046082741659725994213004594338569615
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 451069369 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 451069369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 37.rom_ctrl_stress_all_with_rand_reset.66960777095826895310540114697428296937294684563713906526546149236567469497428
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:33e999db-e7d7-4128-a73b-62d0e956905f
```
  - 45.rom_ctrl_stress_all_with_rand_reset.100766658289859920545289860390773448693430493884373282365556582770547670948474
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e1e06d3c-7711-4269-8420-66dd548686de
```
  - ... and 1 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 32.rom_ctrl_stress_all_with_rand_reset.19338598665344324811743407215240642918888580722195548872069853063958500268767
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10005384836 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xf1957fc5
  UVM_INFO @ 10005384836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.rom_ctrl_stress_all_with_rand_reset.51689436800805257571428088386837208922914627855733985082984313283707593703550
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10008916576 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xcb4f1fd1
  UVM_INFO @ 10008916576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 41.rom_ctrl_stress_all_with_rand_reset.6066735688857363810056137786433599679457558733818638371363206726784287144681
    Line 985, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1491989598282 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 1491989598282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `2cf28c40e5`