ROM_CTRL/32KB Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: `e9ae10fb42`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	37.030s	17.512ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.990s	1.934ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.920s	2.158ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	17.000s	8.556ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.330s	7.793ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.150s	16.412ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.920s	2.158ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.330s	7.793ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.330s	1.838ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.250s	2.063ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	16.310s	3.881ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.665m	10.677ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.010s	8.394ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.530s	2.155ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.740s	2.092ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.740s	2.092ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.990s	1.934ms	5	5	100.00
		rom_ctrl_csr_rw	15.920s	2.158ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.330s	7.793ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.550s	8.150ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.990s	1.934ms	5	5	100.00
		rom_ctrl_csr_rw	15.920s	2.158ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.330s	7.793ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.550s	8.150ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.969m	196.469ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.076m	50.284ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.782m	10.784ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.345m	2.467ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.782m	10.784ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.969m	196.469ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.969m	196.469ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.969m	196.469ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.969m	196.469ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.969m	196.469ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.782m	10.784ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.782m	10.784ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	37.030s	17.512ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	37.030s	17.512ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	37.030s	17.512ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.345m	2.467ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.969m	196.469ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.010s	8.394ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.969m	196.469ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.969m	196.469ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.969m	196.469ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.076m	50.284ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.782m	10.784ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.122h	24.407ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			467	500	93.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.35	96.89	92.42	97.67	100.00	98.62	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 27 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.50310611927398578485040587985147558795483257725630147890547186309322801418655
    Line 428, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22347659697 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 22347659697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.6979384801798599606749715956230595312752598799846848186397269495803645529353
    Line 272, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2390688858 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2390688858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 12.rom_ctrl_stress_all_with_rand_reset.10516649567860077493474409654606964444478390307623510134110779945136302884489
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:7ab7306d-72c4-4169-aac1-168e4b15ef45
```
  - 27.rom_ctrl_stress_all_with_rand_reset.111077799312786665796624815738906556290455595905698600121535251507194855770079
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:519c0d49-74ee-4dbe-9db0-922e1c00cce1
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 19.rom_ctrl_stress_all_with_rand_reset.7248315197278613170933462895150688078911250098772867527881875524791338920651
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12556948015 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xfb5ff81e
  UVM_INFO @ 12556948015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: e9ae10fb42

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e9ae10fb42`