ROM_CTRL/32KB Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	41.330s	3.937ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.900s	5.741ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.350s	4.104ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	13.930s	1.746ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.060s	6.361ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.940s	38.493ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.350s	4.104ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.060s	6.361ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	16.150s	2.121ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.770s	1.845ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.460s	2.120ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.672m	40.679ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.990s	17.499ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	16.750s	2.124ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	21.120s	18.747ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	21.120s	18.747ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.900s	5.741ms	5	5	100.00
		rom_ctrl_csr_rw	16.350s	4.104ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.060s	6.361ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.580s	7.947ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.900s	5.741ms	5	5	100.00
		rom_ctrl_csr_rw	16.350s	4.104ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.060s	6.361ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.580s	7.947ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	6.606m	36.614ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.586m	53.706ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.841m	7.042ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.298m	18.334ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.841m	7.042ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.606m	36.614ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.606m	36.614ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.606m	36.614ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.606m	36.614ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.606m	36.614ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.841m	7.042ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.841m	7.042ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	41.330s	3.937ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	41.330s	3.937ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	41.330s	3.937ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.298m	18.334ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.606m	36.614ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.990s	17.499ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	6.606m	36.614ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.606m	36.614ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	6.606m	36.614ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.586m	53.706ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.841m	7.042ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.510h	212.669ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			468	500	93.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.20	96.89	91.99	97.67	100.00	98.28	97.45	98.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 22 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.51536093478056473868967913527096940504781348893663927426287312407219737634364
    Line 340, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42220127236 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 42220127236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.rom_ctrl_stress_all_with_rand_reset.62728623745949050450832086312091614197114965158832615583245959358631635740096
    Line 574, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39995093973 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 39995093973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 19.rom_ctrl_stress_all_with_rand_reset.10247609807873402389139497642553845970137198072125774975260548033444505392735
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:69d0e6ac-7025-46da-8492-044190cdd287
```
  - 20.rom_ctrl_stress_all_with_rand_reset.25291698341868526669492534916174458957290030844235112706358433601277731803299
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1645cf47-5a34-4d82-b145-e68edde52651
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.15460081630301076729071130623809991449615070723006105189403259047026478259991
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12047792841 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xf0aff1d2
  UVM_INFO @ 12047792841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 32.rom_ctrl_kmac_err_chk.100373429247043409531314521340187758080137127121823318832178379821094336879437
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 3315518673 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 3315518673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `abd7ce57f2`