ROM_CTRL/32KB Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: `e6706fcc7b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	43.480s	4.266ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.120s	25.044ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.540s	10.004ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	17.200s	2.038ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.580s	7.491ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.280s	1.594ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.540s	10.004ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.580s	7.491ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	17.300s	15.089ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.240s	3.658ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.130s	2.160ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.814m	61.274ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.260s	17.428ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	15.240s	8.020ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	21.380s	16.379ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	21.380s	16.379ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.120s	25.044ms	5	5	100.00
		rom_ctrl_csr_rw	16.540s	10.004ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.580s	7.491ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.140s	13.388ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.120s	25.044ms	5	5	100.00
		rom_ctrl_csr_rw	16.540s	10.004ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.580s	7.491ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.140s	13.388ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.868m	86.154ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.475m	11.379ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.823m	4.433ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.319m	3.940ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.823m	4.433ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.868m	86.154ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.868m	86.154ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.868m	86.154ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.868m	86.154ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.868m	86.154ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.823m	4.433ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.823m	4.433ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	43.480s	4.266ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	43.480s	4.266ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	43.480s	4.266ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.319m	3.940ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.868m	86.154ms	49	50	98.00
		rom_ctrl_kmac_err_chk	35.260s	17.428ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.868m	86.154ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.868m	86.154ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.868m	86.154ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.475m	11.379ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.823m	4.433ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.653h	33.658ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			461	500	92.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	96.89	91.99	97.67	100.00	98.28	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 29 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.2021290832598776056886262164329909947357122622901532274078990509614155590725
    Line 803, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 125766318316 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 125766318316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.109290209919502057768188405525514398790453125055793402725119562390423421410154
    Line 439, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 87889273747 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 87889273747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.25864204795718756616933762593428308782914564612451556460887809272136581213100
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:27e0820a-b83c-4b3d-bb7b-efa830141701
```
  - 7.rom_ctrl_stress_all_with_rand_reset.57781581333094558039297975974210813971973123597595239625072596464575416806880
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:222fd572-95e0-4509-b8b9-0ec8f4ce60b8
```
  - ... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 15.rom_ctrl_stress_all_with_rand_reset.102258896841565907195655963904794419655110373673292336106777492328740277894049
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10009155559 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3a63a10e
  UVM_INFO @ 10009155559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.rom_ctrl_stress_all_with_rand_reset.19211109339512349068828931785999026112754817699966139088270617125378198255914
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10016997379 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x51d44ea3
  UVM_INFO @ 10016997379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 21.rom_ctrl_corrupt_sig_fatal_chk.86157950960566048882774915206477792881093561966293560579097576480274817247905
    Line 308, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 38250906433 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 38250906433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all has 1 failures.
  - 48.rom_ctrl_stress_all.59139423479654661561964208007105234082339455628617753162198060026254688794924
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 1702720022 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 1702720022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e6706fcc7b`