ROM_CTRL/32KB Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	36.240s	4.134ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.910s	1.864ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.680s	2.141ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	17.330s	2.117ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.570s	3.241ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.130s	2.084ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.680s	2.141ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.570s	3.241ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	13.620s	1.645ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.070s	7.279ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.710s	2.200ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.611m	11.550ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.240s	8.030ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.590s	8.532ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.440s	2.203ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.440s	2.203ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.910s	1.864ms	5	5	100.00
		rom_ctrl_csr_rw	15.680s	2.141ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.570s	3.241ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.370s	2.003ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.910s	1.864ms	5	5	100.00
		rom_ctrl_csr_rw	15.680s	2.141ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.570s	3.241ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.370s	2.003ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	11.104m	269.394ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.635m	46.602ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.746m	6.825ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.264m	6.304ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.746m	6.825ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.104m	269.394ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.104m	269.394ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	11.104m	269.394ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.104m	269.394ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.104m	269.394ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.746m	6.825ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.746m	6.825ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	36.240s	4.134ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	36.240s	4.134ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	36.240s	4.134ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.264m	6.304ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	11.104m	269.394ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.240s	8.030ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	11.104m	269.394ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.104m	269.394ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	11.104m	269.394ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.635m	46.602ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.746m	6.825ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.244h	247.474ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			468	500	93.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.31	96.89	92.42	97.67	100.00	98.62	97.45	98.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 23 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.105454778720862438700772409037339247060333123746180694860336867680313074672968
    Line 578, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 85477760509 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 85477760509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rom_ctrl_stress_all_with_rand_reset.49363635705809969652055082267872776711381663166974793996189542678258718050908
    Line 344, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18258990650 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 18258990650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 9 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.16962647360610681979508766822598910252164639633636508735586463467674436091012
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:f9713f5e-c226-4b14-904c-ec678efde4b1
```
  - 7.rom_ctrl_stress_all_with_rand_reset.39249275183483922650244145206573328620889917737500873662124038424172287103788
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:50c4ed51-0ea7-4cf0-95f8-de5547e4a1c2
```
  - ... and 7 more failures.

ROM_CTRL/32KB Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `3e678c112b`