ROM_CTRL/32KB Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: `9edf84e236`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	44.300s	4.050ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	14.380s	4.850ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.430s	8.911ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.370s	2.459ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.020s	6.559ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.640s	2.146ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.430s	8.911ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.020s	6.559ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.890s	1.921ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.280s	5.898ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.780s	2.219ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.592m	46.115ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.100s	27.458ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.960s	2.063ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	21.040s	2.780ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	21.040s	2.780ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	14.380s	4.850ms	5	5	100.00
		rom_ctrl_csr_rw	16.430s	8.911ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.020s	6.559ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.280s	2.062ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	14.380s	4.850ms	5	5	100.00
		rom_ctrl_csr_rw	16.430s	8.911ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.020s	6.559ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.280s	2.062ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.609m	307.120ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.599m	48.331ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.829m	4.603ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.343m	683.888us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.829m	4.603ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.609m	307.120ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.609m	307.120ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.609m	307.120ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.609m	307.120ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.609m	307.120ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.829m	4.603ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.829m	4.603ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	44.300s	4.050ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	44.300s	4.050ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	44.300s	4.050ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.343m	683.888us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.609m	307.120ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.100s	27.458ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.609m	307.120ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.609m	307.120ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.609m	307.120ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.599m	48.331ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.829m	4.603ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.187h	43.329ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			464	500	92.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.51	96.89	92.56	97.67	100.00	98.97	97.45	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 26 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.62201625431799064169655435761758739568669094855765696928552376284455014257330
    Line 299, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10357841735 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10357841735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.110336773535712066582218400131050781432998236983234309418081679912360583722881
    Line 306, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17819175120 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17819175120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.68988431382110928787570872606348012747672673128905002860596246718700382152128
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:11e92fc2-51fb-472f-8ebf-b305ce487bf6
```
  - 2.rom_ctrl_stress_all_with_rand_reset.105329008197964852652826802659599767727871701705419709465117960267422956758381
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:daa3a6a0-b5ea-4fa1-bf0e-c01fd80283aa
```
  - ... and 5 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.72749152317132345886830714388301227292198661840861158769857057852967102803627
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10013125028 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x22ea2325
  UVM_INFO @ 10013125028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.rom_ctrl_stress_all_with_rand_reset.65227729768124126436292351357328636893682529873392668071929977013520996063632
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10014046253 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x32e5cc43
  UVM_INFO @ 10014046253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 35.rom_ctrl_stress_all.48371622740825195457850676801665881306436678269144169678190943260858242725383
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 5671586388 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 5671586388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `9edf84e236`